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author | Prem Shanker Jha <premjha2@in.ibm.com> | 2016-06-08 05:48:31 -0500 |
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committer | Daniel M. Crowell <dcrowell@us.ibm.com> | 2017-03-01 13:58:01 -0500 |
commit | d3d4ae7c89e6b35fffa8857170762992dc3c6538 (patch) | |
tree | fbdb27d57e114993d527ff5b43f12e285ad8eb66 /src/import/hwpf/fapi2 | |
parent | aba5dad89d16464fbf1a9228f5c44c5972e9d070 (diff) | |
download | talos-hostboot-d3d4ae7c89e6b35fffa8857170762992dc3c6538.tar.gz talos-hostboot-d3d4ae7c89e6b35fffa8857170762992dc3c6538.zip |
PM: Added support for PGPE Boot/PGPE integration
- support for P-State parameter block
- implements a compact image layout of PGPE similar to CME/SGPE.
- adds PGPE boot progress code as a field in PPMR header.
- implements PGPE boot loader and PGPE boot copier.
- incorporates ability to generate PPMR header in the build flow.
- change logic for calculating CME's first block copy length.
- Turned on generated tables in PGPE Hcode
- Fixed up pointers to generated tables
- add ATTR_PGPE_HCODE_FUNCTION_ENABLE attribute to control PGPE ops
- fix p9_pstate_parameter_build bug with AVS timing attributes
- Make OCC Pstate Parameter block a fixed offset (128KB) in PPMR
- Make Pstate Table from PGPE a fixed offset (144KB) in PPMR to ease debug
- Fix Endianes issues in OCC PPB and input slope calcs
- Added PGPE Hcode Length to PGPE header so that GPPB SRAM location is known.
- Build flag for OCc Immediate IPC response
- Build flag to no use temp boot settings
- Expanding tracing for debug
- Added default values for PBAX attributes as placeholders for MRW in firmware
- Added WOF VFRT structure definions to headers; movement into HOMER NOT
yet supported
- Addressed review comments and rebased
- Rebased with ATTR_PGPE_HCODE_FUNCTION_ENABLE in separate commit for Cronus
Change-Id: I4752debbc7fb3275d4e79804333654511de427ff
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/26115
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Reviewed-by: Gregory S. Still <stillgs@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: ASHISH A. MORE <ashish.more@in.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/26116
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Diffstat (limited to 'src/import/hwpf/fapi2')
-rw-r--r-- | src/import/hwpf/fapi2/xml/attribute_info/hb_temp_defaults.xml | 51 |
1 files changed, 25 insertions, 26 deletions
diff --git a/src/import/hwpf/fapi2/xml/attribute_info/hb_temp_defaults.xml b/src/import/hwpf/fapi2/xml/attribute_info/hb_temp_defaults.xml index fef970bc2..620da1d3d 100644 --- a/src/import/hwpf/fapi2/xml/attribute_info/hb_temp_defaults.xml +++ b/src/import/hwpf/fapi2/xml/attribute_info/hb_temp_defaults.xml @@ -60,7 +60,6 @@ <id>ATTR_MSS_MRW_SAFEMODE_MEM_THROTTLED_N_COMMANDS_PER_PORT</id> <default>32</default> </attribute> - <attribute> <id>ATTR_MSS_MRW_REFRESH_RATE_REQUEST</id> <default>0</default> @@ -74,32 +73,32 @@ <default>0x1</default> </attribute> + <attribute> + <id>ATTR_SECTOR_BUFFER_STRENGTH</id> + </attribute> + <attribute> + <id>ATTR_PULSE_MODE_ENABLE</id> + </attribute> + <attribute> + <id>ATTR_PULSE_MODE_VALUE</id> + </attribute> + <attribute> + <id>ATTR_MSS_MRW_DRAM_WRITE_CRC</id> + <default>0x0</default> + </attribute> + <attribute> + <id>ATTR_MSS_MRW_TEMP_REFRESH_MODE</id> + <default>0x0</default> + </attribute> + <attribute> + <id>ATTR_PERF_24x7_INVOCATION_TIME_MS</id> + <default>0x1</default> + </attribute> <attribute> - <id>ATTR_SECTOR_BUFFER_STRENGTH</id> - </attribute> - <attribute> - <id>ATTR_PULSE_MODE_ENABLE</id> - </attribute> - <attribute> - <id>ATTR_PULSE_MODE_VALUE</id> - </attribute> - <attribute> - <id>ATTR_MSS_MRW_DRAM_WRITE_CRC</id> - <default>0x0</default> - </attribute> - <attribute> - <id>ATTR_MSS_MRW_TEMP_REFRESH_MODE</id> - <default>0x0</default> - </attribute> - <attribute> - <id>ATTR_PERF_24x7_INVOCATION_TIME_MS</id> - <default>0x1</default> - </attribute> - <attribute> - <id>ATTR_PGPE_HCODE_FUNCTION_ENABLE</id> - <!-- this setting enables the OCC Immediate Resp Mode Only --> - <default>0x0</default> - </attribute> + <id>ATTR_PGPE_HCODE_FUNCTION_ENABLE</id> + <!-- this setting enables the OCC Immediate Resp Mode Only --> + <default>0x0</default> + </attribute> <attribute> <id>ATTR_IO_OBUS_DCCAL_FLAGS</id> <default>0x0</default> |