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| author | Andre Marin <aamarin@us.ibm.com> | 2019-02-19 11:06:18 -0600 |
|---|---|---|
| committer | Christian R. Geddes <crgeddes@us.ibm.com> | 2019-03-01 10:18:10 -0600 |
| commit | 877a032b90cd231cb7a75df4b29955b957a8f06b (patch) | |
| tree | 6103149aeb717b717deb9091bc19489dcbd4fcb2 /src/import/generic/memory/lib | |
| parent | dadbba56f4139332f5f3dd3706ce2e76ef6845b8 (diff) | |
| download | talos-hostboot-877a032b90cd231cb7a75df4b29955b957a8f06b.tar.gz talos-hostboot-877a032b90cd231cb7a75df4b29955b957a8f06b.zip | |
Fix SPD cas latency assert bug
Change-Id: Ic38888f6db211e16385f5223ff267fd7044c6758
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/72250
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Louis Stermole <stermole@us.ibm.com>
Reviewed-by: STEPHEN GLANCY <sglancy@us.ibm.com>
Dev-Ready: ANDRE A. MARIN <aamarin@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/72316
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>
Diffstat (limited to 'src/import/generic/memory/lib')
| -rw-r--r-- | src/import/generic/memory/lib/spd/common/ddr4/spd_decoder_ddr4.H | 16 |
1 files changed, 12 insertions, 4 deletions
diff --git a/src/import/generic/memory/lib/spd/common/ddr4/spd_decoder_ddr4.H b/src/import/generic/memory/lib/spd/common/ddr4/spd_decoder_ddr4.H index f4e97a7c7..12821c76f 100644 --- a/src/import/generic/memory/lib/spd/common/ddr4/spd_decoder_ddr4.H +++ b/src/import/generic/memory/lib/spd/common/ddr4/spd_decoder_ddr4.H @@ -1189,11 +1189,19 @@ class decoder<DDR4, BASE_CNFG, R> : public base_cnfg_decoder right_aligned_insert(l_buffer, l_fourth_raw_byte, l_third_raw_byte, l_sec_raw_byte, l_first_raw_byte); // According to the JEDEC spec: - // Byte 22 (Bits 7~0) and Byte 23 are reserved and thus not supported - // Check for a valid value - constexpr size_t MAX_VALID_VAL = 0x3FFFF; + // Byte 22 (Bits 7~0) and Byte 23 are reserved in the base revision SPD general section + // Only bit 6 (right-aligned) for Byte 23 is reserved for subsequent SPD revisions + // Check for a valid value, and that reserved bit is not set + // We return Byte 23 arbitrarily as the failed byte, but any byte (20 - 23) would work + constexpr size_t MAX_VALID_VAL = (R == rev::V1_0) ? 0x0003FFFF : 0xBFFFFFFF; + + constexpr uint64_t DATA_START_OFFSET = 32; + constexpr uint64_t RESERVED_BIT = DATA_START_OFFSET + 1; + // Bit 6 of byte 23 must be 0 (reserved for future use) + const bool RESERVED_BIT_VALUE = l_buffer.getBit<RESERVED_BIT>(); + FAPI_TRY( mss::check::invalid_value(iv_target, - l_buffer <= MAX_VALID_VAL, + l_buffer <= MAX_VALID_VAL && !RESERVED_BIT_VALUE, 23, l_buffer, mss::BAD_SPD_DATA, |
