Add in RCD attributes for DD2 debug

Change-Id: Ibd8e3bf3d75982fd14584fbd47b74979d515ea39
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/42090
Reviewed-by: STEPHEN GLANCY <sglancy@us.ibm.com>
Reviewed-by: Louis Stermole <stermole@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Reviewed-by: Brent Wieman <bwieman@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/42133
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Reviewed-by: Dean Sanner <dsanner@us.ibm.com>

3 files changed, 108 insertions, 0 deletions

diff --git a/src/import/generic/memory/lib/spd/common/ddr4/spd_decoder_ddr4.H b/src/import/generic/memory/lib/spd/common/ddr4/spd_decoder_ddr4.H
index 63584075f..237e63378 100644
--- a/src/import/generic/memory/lib/spd/common/ddr4/spd_decoder_ddr4.H
+++ b/src/import/generic/memory/lib/spd/common/ddr4/spd_decoder_ddr4.H
@@ -1154,6 +1154,29 @@ class decoder_v1_0 : public decoder
         /// @note Page 4.1.2.12 - 54
         ///
         virtual fapi2::ReturnCode dram_manufacturer_id_code( uint16_t& o_output ) const override;
+
+        ///
+        /// @brief Decodes RCD Manufacturer ID code
+        /// @param[out] o_value rcd manufacturing id code
+        /// @return FAPI2_RC_SUCCESS if okay
+        /// @note SPD Byte 133 134
+        /// @note Item JEDEC Standard No. 21-C
+        /// @note DDR4 SPD Document Release 2
+        /// @note Page 4.1.2.12 - 54
+        ///
+        virtual fapi2::ReturnCode reg_manufacturer_id_code( uint16_t& o_value ) const override;
+
+        ///
+        /// @brief Decodes Register Revision Number
+        /// @param[out] o_value register revision number
+        /// @return FAPI2_RC_SUCCESS if okay
+        /// @note SPD Byte 135
+        /// @note Item JEDEC Standard No. 21-C
+        /// @note DDR4 SPD Document Release 2
+        /// @note Page 4.1.2.12 - 54
+        ///
+        virtual fapi2::ReturnCode register_rev_num( uint8_t& o_value ) const override;
+
         ///
         /// @brief Decodes DRAM Stepping
         /// @param[out] o_value uint8_t DRAM Stepping val
diff --git a/src/import/generic/memory/lib/spd/common/ddr4/spd_decoder_ddr4_v1_0.C b/src/import/generic/memory/lib/spd/common/ddr4/spd_decoder_ddr4_v1_0.C
index baca956f8..845648752 100644
--- a/src/import/generic/memory/lib/spd/common/ddr4/spd_decoder_ddr4_v1_0.C
+++ b/src/import/generic/memory/lib/spd/common/ddr4/spd_decoder_ddr4_v1_0.C
@@ -2866,6 +2866,69 @@ fapi2::ReturnCode decoder_v1_0::dram_manufacturer_id_code( uint16_t& o_value ) c
 }
 
 ///
+/// @brief Decodes REGISTER Manufacturer ID code
+/// @param[out] o_value rcd manufacturing id code
+/// @return FAPI2_RC_SUCCESS if okay
+/// @note SPD Byte 133-134
+/// @note Item JEDEC Standard No. 21-C
+/// @note DDR4 SPD Document Release 2
+/// @note Page 4.1.2.12 - 54
+///
+fapi2::ReturnCode decoder_v1_0::reg_manufacturer_id_code( uint16_t& o_value ) const
+{
+    constexpr size_t BYTE_INDEX_LSB = 133;
+    uint8_t mfgid_LSB = iv_spd_data[BYTE_INDEX_LSB];
+
+    constexpr size_t BYTE_INDEX_MSB = 134;
+    uint8_t mfgid_MSB = iv_spd_data[BYTE_INDEX_MSB];
+
+    constexpr size_t MSB_START = 0;
+    constexpr size_t MSB_LEN = 8;
+    constexpr size_t LSB_START = 8;
+    constexpr size_t LSB_LEN = 8;
+
+    fapi2::buffer<uint16_t> l_buffer;
+    l_buffer.insertFromRight<MSB_START, MSB_LEN>( mfgid_MSB )
+    .insertFromRight<LSB_START, LSB_LEN>( mfgid_LSB );
+
+    o_value = l_buffer;
+
+    FAPI_INF("%s.RCD Manufacturer ID Code (rcd_mfg_id): %x",
+             mss::c_str(iv_target),
+             o_value);
+
+    return fapi2::FAPI2_RC_SUCCESS;
+}
+
+///
+/// @brief Decodes Register Revision Number
+/// @param[out] o_value register revision number
+/// @return FAPI2_RC_SUCCESS if okay
+/// @note SPD Byte 135
+/// @note Item JEDEC Standard No. 21-C
+/// @note DDR4 SPD Document Release 2
+/// @note Page 4.1.2.12 - 54
+///
+fapi2::ReturnCode decoder_v1_0::register_rev_num( uint8_t& o_value ) const
+{
+    // Trace in the front assists w/ debug
+    constexpr size_t BYTE_INDEX = 135;
+
+    FAPI_INF("%s SPD data at Byte %d: 0x%01X.",
+             mss::c_str(iv_target),
+             BYTE_INDEX,
+             iv_spd_data[BYTE_INDEX]);
+
+    o_value = iv_spd_data[BYTE_INDEX];
+
+    FAPI_INF("%s. Register Revision Number: %x",
+             mss::c_str(iv_target),
+             o_value);
+
+    return fapi2::FAPI2_RC_SUCCESS;
+}
+
+///
 /// @brief Decodes DRAM Stepping
 /// @param[out] o_value uint8_t  DRAM Stepping val
 /// @return FAPI2_RC_SUCCESS if okay
diff --git a/src/import/generic/memory/lib/spd/common/spd_decoder_base.H b/src/import/generic/memory/lib/spd/common/spd_decoder_base.H
index c61983436..76594ba66 100644
--- a/src/import/generic/memory/lib/spd/common/spd_decoder_base.H
+++ b/src/import/generic/memory/lib/spd/common/spd_decoder_base.H
@@ -871,6 +871,28 @@ class decoder
         }
 
         ///
+        /// @brief Decodes RCD Manufacturer ID code
+        /// @param[out] o_value rcd manufacturing id code
+        /// @return FAPI2_RC_SUCCESS if okay
+        ///
+        virtual fapi2::ReturnCode reg_manufacturer_id_code( uint16_t& o_value ) const
+        {
+            o_value = 0;
+            return fapi2::FAPI2_RC_SUCCESS;
+        }
+
+        ///
+        /// @brief Decodes Register Revision Number
+        /// @param[out] o_value register revision number
+        /// @return FAPI2_RC_SUCCESS if okay
+        ///
+        virtual fapi2::ReturnCode register_rev_num( uint8_t& o_value ) const
+        {
+            o_value = 0;
+            return fapi2::FAPI2_RC_SUCCESS;
+        }
+
+        ///
         /// @brief Decodes DRAM Stepping
         /// @param[out] o_value uint8_t DRAM Stepping val
         /// @return FAPI2_RC_SUCCESS if okay