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author | Andre Marin <aamarin@us.ibm.com> | 2019-07-11 13:01:31 -0400 |
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committer | Daniel M Crowell <dcrowell@us.ibm.com> | 2019-08-09 07:56:28 -0500 |
commit | 1061da0271bf85fe29fedff6f242181b3dc6d5ed (patch) | |
tree | f586bdbba79f3ee934073e1bbd49981d0d29b0b0 /src/import/generic/memory/lib/spd/spd_fields_ddr4.H | |
parent | 9fb424b8af396bb626c28105b4383fc22aeccd94 (diff) | |
download | talos-hostboot-1061da0271bf85fe29fedff6f242181b3dc6d5ed.tar.gz talos-hostboot-1061da0271bf85fe29fedff6f242181b3dc6d5ed.zip |
Add missing attributes needed to be set for generic mss_kind
Setting DRAM_MFG_ID, RCD_MFG_ID, and MODULE_HEIGHT
to eff_config and editing SPD timing values to use common
API for calculations that come with values from
the EEPROM
Change-Id: If33f2f2a49a62f114575ef36d6325fc537d1dc27
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/79921
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Reviewed-by: Louis Stermole <stermole@us.ibm.com>
Reviewed-by: STEPHEN GLANCY <sglancy@us.ibm.com>
Reviewed-by: Jennifer A Stofer <stofer@us.ibm.com>
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/79936
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M Crowell <dcrowell@us.ibm.com>
Diffstat (limited to 'src/import/generic/memory/lib/spd/spd_fields_ddr4.H')
-rw-r--r-- | src/import/generic/memory/lib/spd/spd_fields_ddr4.H | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/src/import/generic/memory/lib/spd/spd_fields_ddr4.H b/src/import/generic/memory/lib/spd/spd_fields_ddr4.H index 6739276cb..194eba510 100644 --- a/src/import/generic/memory/lib/spd/spd_fields_ddr4.H +++ b/src/import/generic/memory/lib/spd/spd_fields_ddr4.H @@ -1176,6 +1176,12 @@ class fields<DDR4, DDIMM_MODULE> PMIC1_PHASE_COMBIN_BYTE = 259, PMIC1_PHASE_COMBIN_START = 4, PMIC1_PHASE_COMBIN_LEN = 4, + + // Byte 552-553 + DRAM_MFR_ID_CODE_LSB_BYTE = 552, + DRAM_MFR_ID_CODE_MSB_BYTE = 553, + DRAM_MFR_ID_CODE_START = 0, + DRAM_MFR_ID_CODE_LEN = 8, }; public: @@ -1408,6 +1414,9 @@ class fields<DDR4, DDIMM_MODULE> // Byte 259: PMIC1 Phase Combination static constexpr field_t PMIC1_PHASE_COMBIN{PMIC1_PHASE_COMBIN_BYTE, PMIC1_PHASE_COMBIN_START, PMIC1_PHASE_COMBIN_LEN}; + // Byte 552 and 553: DRAM manufacturing ID for DDIMMs + static constexpr field_t DRAM_MFR_ID_CODE_LSB{DRAM_MFR_ID_CODE_LSB_BYTE, DRAM_MFR_ID_CODE_START, DRAM_MFR_ID_CODE_LEN}; + static constexpr field_t DRAM_MFR_ID_CODE_MSB{DRAM_MFR_ID_CODE_MSB_BYTE, DRAM_MFR_ID_CODE_START, DRAM_MFR_ID_CODE_LEN}; }; }// spd |