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| author | Rahul Batra <rbatra@us.ibm.com> | 2018-01-04 21:43:15 -0600 |
|---|---|---|
| committer | Daniel M. Crowell <dcrowell@us.ibm.com> | 2018-04-03 14:01:13 -0400 |
| commit | da512cac4ed43ab674545df891c736d1e8204208 (patch) | |
| tree | 412dd030a3a80d9b1ec1bb04ceaae42f12d066ae /src/import/chips | |
| parent | 8e5461d3b3609aa630d65ea256a7f44b477a4771 (diff) | |
| download | talos-hostboot-da512cac4ed43ab674545df891c736d1e8204208.tar.gz talos-hostboot-da512cac4ed43ab674545df891c736d1e8204208.zip | |
PGPE: Error Handling Support
Key_Cronus_Test=PM_REGRESS
Change-Id: I00aca629108aeaca88db34eec8e408f3cd48ff7f
CQ: SW414842
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/48635
Reviewed-by: RANGANATHPRASAD G. BRAHMASAMUDRA <prasadbgr@in.ibm.com>
Reviewed-by: YUE DU <daviddu@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Tested-by: Cronus HW CI <cronushw-ci+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Gregory S. Still <stillgs@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/51525
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Diffstat (limited to 'src/import/chips')
| -rw-r--r-- | src/import/chips/p9/common/pmlib/include/pstate_pgpe_occ_api.h | 2 | ||||
| -rw-r--r-- | src/import/chips/p9/procedures/hwp/lib/p9_pm_hcd_flags.h | 67 |
2 files changed, 40 insertions, 29 deletions
diff --git a/src/import/chips/p9/common/pmlib/include/pstate_pgpe_occ_api.h b/src/import/chips/p9/common/pmlib/include/pstate_pgpe_occ_api.h index 9b77548eb..3be2df6ef 100644 --- a/src/import/chips/p9/common/pmlib/include/pstate_pgpe_occ_api.h +++ b/src/import/chips/p9/common/pmlib/include/pstate_pgpe_occ_api.h @@ -68,6 +68,8 @@ enum MESSAGE_ID_IPI2HI // to using the new VFRT. The original VFRT is still being used. #define PGPE_WOF_RC_VFRT_QUAD_MISMATCH 0x20 #define PGPE_RC_REQ_WHILE_PENDING_ACK 0x21 +#define PGPE_RC_NULL_VFRT_POINTER 0x22 +#define PGPE_RC_INVALID_PMCR_OWNER 0x23 // // PMCR Owner diff --git a/src/import/chips/p9/procedures/hwp/lib/p9_pm_hcd_flags.h b/src/import/chips/p9/procedures/hwp/lib/p9_pm_hcd_flags.h index bdee71344..925916040 100644 --- a/src/import/chips/p9/procedures/hwp/lib/p9_pm_hcd_flags.h +++ b/src/import/chips/p9/procedures/hwp/lib/p9_pm_hcd_flags.h @@ -57,8 +57,8 @@ enum PM_GPE_OCCFLG_DEFS SGPE_IGNORE_STOP_ACTION = 10, SGPE_IGNORE_STOP_EXITS = 11, SGPE_IGNORE_STOP_ENTRIES = 12, - SGPE_24_7_ACTIVATE = 14, - SGPE_24_7_ACTIVE = 15, + AUX_THREAD_ACTIVATE = 14, + AUX_THREAD_ACTIVE = 15, PIB_I2C_MASTER_ENGINE_1_LOCK_BIT0 = 16, //BIT0 ored BIT1 gives the field PIB_I2C_MASTER_ENGINE_1_LOCK_BIT1 = 17, //BIT0 ored BIT1 gives the field PIB_I2C_MASTER_ENGINE_2_LOCK_BIT0 = 18, //BIT0 ored BIT1 gives the field @@ -75,8 +75,13 @@ enum PM_GPE_OCCFLG_DEFS //Enum form of OCC FLAG2. enum PM_GPE_OCCFLG2_DEFS { + OCCFLG2_DEAD_CORES_START = 0, + OCCFLG2_DEAD_CORES_LENGTH = 24, + OCCFLG2_PGPE_HCODE_FIT_ERR_INJ = 27, PM_CALLOUT_ACTIVE = 28, - STOP_RECOVERY_TRIGGER_ENABLE = 29 + STOP_RECOVERY_TRIGGER_ENABLE = 29, + OCCFLG2_SGPE_HCODE_STOP_REQ_ERR_INJ = 30, + OCCFLG2_PGPE_HCODE_PSTATE_REQ_ERR_INJ = 31 }; // @@ -92,11 +97,12 @@ enum PM_GPE_OCC_SCRATCH2_DEFS CME_DEBUG_TRAP_ENABLE = 9, PGPE_DEBUG_TRAP_ENABLE = 10, L3_CONTAINED_MODE = 11, - PGPE_SAFE_MODE_ERROR = 12, + PGPE_SAFE_MODE_ERROR = 14, PM_DEBUG_HALT_ENABLE = 15, CORE_THROTTLE_CONTINUOUS_CHANGE_ENABLE = 16, PGPE_OP_TRACE_DISABLE = 24, PGPE_OP_TRACE_MEM_MODE = 25 + }; // @@ -104,31 +110,32 @@ enum PM_GPE_OCC_SCRATCH2_DEFS // enum PM_CME_FLAGS_DEFS { - CME_FLAGS_STOP_READY = 0, - CME_FLAGS_PMCR_READY = 1, - CME_FLAGS_QMGR_READY = 2, - CME_FLAGS_QMGR_MASTER = 3, - CME_FLAGS_RCLK_OPERABLE = 4, - CME_FLAGS_IVRM_OPERABLE = 5, - CME_FLAGS_VDM_OPERABLE = 6, - CME_FLAGS_OCC_HB_SAFE_MODE = 7, - CME_FLAGS_STOP_BLOCK_EXIT_C0 = 8, - CME_FLAGS_STOP_BLOCK_EXIT_C1 = 9, - CME_FLAGS_STOP_BLOCK_ENTRY_C0 = 10, - CME_FLAGS_STOP_BLOCK_ENTRY_C1 = 11, - CME_FLAGS_CORE_QUIESCE_ACTIVE = 12, - CME_FLAGS_PM_DEBUG_HALT_ENABLE = 13, - CME_FLAGS_WAIT_ON_PSTATE_START = 14, - CME_FLAGS_SPWU_CHECK_ENABLE = 22, - CME_FLAGS_BLOCK_ENTRY_STOP11 = 23, - CME_FLAGS_PSTATES_ENABLED = 24, - CME_FLAGS_FREQ_UPDT_DISABLE = 25, - CME_FLAGS_EX_ID = 26, - CME_FLAGS_SIBLING_FUNCTIONAL = 27, - CME_FLAGS_STOP_ENTRY_FIRST_C0 = 28, - CME_FLAGS_STOP_ENTRY_FIRST_C1 = 29, - CME_FLAGS_CORE0_GOOD = 30, - CME_FLAGS_CORE1_GOOD = 31 + CME_FLAGS_STOP_READY = 0, + CME_FLAGS_PMCR_READY = 1, + CME_FLAGS_QMGR_READY = 2, + CME_FLAGS_QMGR_MASTER = 3, + CME_FLAGS_RCLK_OPERABLE = 4, + CME_FLAGS_IVRM_OPERABLE = 5, + CME_FLAGS_VDM_OPERABLE = 6, + CME_FLAGS_PGPE_HB_LOSS_SAFE_MODE = 7, + CME_FLAGS_STOP_BLOCK_EXIT_C0 = 8, + CME_FLAGS_STOP_BLOCK_EXIT_C1 = 9, + CME_FLAGS_STOP_BLOCK_ENTRY_C0 = 10, + CME_FLAGS_STOP_BLOCK_ENTRY_C1 = 11, + CME_FLAGS_CORE_QUIESCE_ACTIVE = 12, + CME_FLAGS_PM_DEBUG_HALT_ENABLE = 13, + CME_FLAGS_SAFE_MODE = 16, + CME_FLAGS_PSTATES_SUSPENDED = 17, + CME_FLAGS_SPWU_CHECK_ENABLE = 22, + CME_FLAGS_BLOCK_ENTRY_STOP11 = 23, + CME_FLAGS_PSTATES_ENABLED = 24, + CME_FLAGS_FREQ_UPDT_DISABLE = 25, + CME_FLAGS_EX_ID = 26, + CME_FLAGS_SIBLING_FUNCTIONAL = 27, + CME_FLAGS_STOP_ENTRY_FIRST_C0 = 28, + CME_FLAGS_STOP_ENTRY_FIRST_C1 = 29, + CME_FLAGS_CORE0_GOOD = 30, + CME_FLAGS_CORE1_GOOD = 31 }; // @@ -147,6 +154,8 @@ enum PM_CME_SCRATCH_DEFS // enum PM_CPPM_CSAR_DEFS { + CPPM_CSAR_FIT_HCODE_ERROR_INJECT = 27, + CPPM_CSAR_ENABLE_PSTATE_REGISTRATION_INTERLOCK = 28, CPPM_CSAR_DISABLE_CME_NACK_ON_PROLONGED_DROOP = 29, CPPM_CSAR_PSTATE_HCODE_ERROR_INJECT = 30, CPPM_CSAR_STOP_HCODE_ERROR_INJECT = 31 |
