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| author | Soma BhanuTej <soma.bhanu@in.ibm.com> | 2018-03-15 03:14:41 -0400 |
|---|---|---|
| committer | Daniel M. Crowell <dcrowell@us.ibm.com> | 2018-03-26 13:13:23 -0400 |
| commit | c4bd7604071fc1780625de6dcf9ceacda1ccad67 (patch) | |
| tree | 75d19b991a597b9ea6a98f118e26d19fa573b2e0 /src/import/chips | |
| parent | fe61cf0701e0208c6fd32e328a90b1061654372c (diff) | |
| download | talos-hostboot-c4bd7604071fc1780625de6dcf9ceacda1ccad67.tar.gz talos-hostboot-c4bd7604071fc1780625de6dcf9ceacda1ccad67.zip | |
Mask off bit 26 of TP_LFIR on FSP machines
Change-Id: Ided77a0645e4f657b326ba5ec63f7c35ab6b2029
CQ: SW421112
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55906
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55908
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Diffstat (limited to 'src/import/chips')
| -rw-r--r-- | src/import/chips/p9/procedures/hwp/perv/p9_sbe_common.C | 9 |
1 files changed, 8 insertions, 1 deletions
diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_common.C b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_common.C index 765a6f548..e0253df15 100644 --- a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_common.C +++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_common.C @@ -742,6 +742,7 @@ fapi2::ReturnCode p9_sbe_common_configure_chiplet_FIR( { uint8_t l_unit_idx; fapi2::buffer<uint64_t> l_scom_data; + FAPI_INF("p9_sbe_common_configure_chiplet_FIR: Entering ..."); FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_UNIT_POS, i_target_chiplet, l_unit_idx), @@ -770,7 +771,13 @@ fapi2::ReturnCode p9_sbe_common_configure_chiplet_FIR( if(l_unit_idx == 0) //TP chiplet { - l_scom_data.clearBit<26>(); //Clear LFIR Mask bit 26 of TP + auto l_target_chip = i_target_chiplet.getParent<fapi2::TARGET_TYPE_PROC_CHIP>(); + fapi2::buffer<uint8_t> l_has_sp; + FAPI_DBG("Reading ATTR_IS_SP_MODE"); + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_IS_SP_MODE, l_target_chip, l_has_sp)); + + //Clear LFIR Mask bit 26 of TP only in FSP less system + l_scom_data.writeBit<26>(l_has_sp.getBit<7>()); } #endif |
