Add MC periodics

Change-Id: I850ad0e5a4bb7bee5c875004bfcbf10b0d112bb4
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/24940
Tested-by: Jenkins Server
Reviewed-by: ANDRE A. MARIN <aamarin@us.ibm.com>
Tested-by: Hostboot CI
Reviewed-by: STEPHEN GLANCY <sglancy@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/24941
Tested-by: FSP CI Jenkins
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>

7 files changed, 20 insertions, 287 deletions

diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/ccs/ccs.H b/src/import/chips/p9/procedures/hwp/memory/lib/ccs/ccs.H
index 3e9f0ea26..3fac32501 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/ccs/ccs.H
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/ccs/ccs.H
@@ -36,7 +36,7 @@
 
 #include <lib/utils/poll.H>
 #include <lib/utils/swizzle.H>
-#include <lib/port/port.H>
+#include <lib/mc/port.H>
 #include <lib/shared/mss_const.H>
 
 // I have a dream that the CCS engine code can be shared among controllers. So, I drive the
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/rank.C b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/rank.C
index 14b5db026..af069f786 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/rank.C
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/rank.C
@@ -150,6 +150,7 @@ fapi2::ReturnCode primary_ranks( const fapi2::Target<TARGET_TYPE_MCA>& i_target,
         FAPI_TRY( mss::eff_num_ranks_per_dimm(d, l_rank_count[mss::index(d)]) );
     }
 
+    FAPI_DBG("ranks: %d, %d", l_rank_count[0], l_rank_count[1]);
     o_rps = primary_rank_pairs[l_rank_count[1]][l_rank_count[0]];
 
 fapi_try_exit:
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/eff_config/eff_config.C b/src/import/chips/p9/procedures/hwp/memory/lib/eff_config/eff_config.C
index d7eaa90bd..72f23c995 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/eff_config/eff_config.C
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/eff_config/eff_config.C
@@ -2691,7 +2691,13 @@ fapi2::ReturnCode eff_config::zqcal_interval(const fapi2::Target<fapi2::TARGET_T
 
     FAPI_TRY( eff_zqcal_interval(l_mcs, l_attrs_zqcal_interval.data()) );
 
-    l_attrs_zqcal_interval[l_port_num] = 0x00;
+
+    // Calculate ZQCAL Interval based on the following equation from Ken:
+    //               0.5
+    // ------------------------------ = 13.333ms
+    //     (1.5 * 10) + (0.15 * 150)
+    //  (13333 * ATTR_MSS_FREQ) / 2
+    l_attrs_zqcal_interval[l_port_num] = 0xF42270;
 
     FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_EFF_ZQCAL_INTERVAL,
                             l_mcs,
@@ -2721,7 +2727,9 @@ fapi2::ReturnCode eff_config::memcal_interval(const fapi2::Target<fapi2::TARGET_
 
     FAPI_TRY( eff_memcal_interval(l_mcs, l_attrs_memcal_interval.data()) );
 
-    l_attrs_memcal_interval[l_port_num] = 0x00;
+    // Calculate MEMCAL Interval based on 1sec interval across all bits per DP16
+    // (62500 * ATTR_MSS_FREQ) / 2
+    l_attrs_memcal_interval[l_port_num] = 0x47868C0;
 
     FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_EFF_MEMCAL_INTERVAL,
                             l_mcs,
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/mss.H b/src/import/chips/p9/procedures/hwp/memory/lib/mss.H
index 61d593167..f8af344ee 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/mss.H
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/mss.H
@@ -53,8 +53,6 @@
 #include <lib/ccs/ccs.H>
 #include <lib/mcbist/mcbist.H>
 
-#include <lib/port/port.H>
-
 #include <lib/dimm/rcd_load.H>
 #include <lib/dimm/mrs_load.H>
 #include <lib/dimm/rank.H>
@@ -66,8 +64,7 @@
 #include <lib/phy/write_cntrl.H>
 #include <lib/phy/read_cntrl.H>
 
-#include <lib/utils/dump_regs.H>
-
 #include <lib/mc/mc.H>
+#include <lib/mc/port.H>
 
 #endif
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/port/port.H b/src/import/chips/p9/procedures/hwp/memory/lib/port/port.H
deleted file mode 100644
index 701fea677..000000000
--- a/src/import/chips/p9/procedures/hwp/memory/lib/port/port.H
+++ /dev/null
@@ -1,280 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: chips/p9/procedures/hwp/memory/lib/port/port.H $              */
-/*                                                                        */
-/* IBM CONFIDENTIAL                                                       */
-/*                                                                        */
-/* EKB Project                                                            */
-/*                                                                        */
-/* COPYRIGHT 2015,2016                                                    */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* The source code for this program is not published or otherwise         */
-/* divested of its trade secrets, irrespective of what has been           */
-/* deposited with the U.S. Copyright Office.                              */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-
-///
-/// @file port.H
-/// @brief Code to support ports
-///
-// *HWP HWP Owner: Brian Silver <bsilver@us.ibm.com>
-// *HWP HWP Backup: Andre Marin <aamarin@us.ibm.com>
-// *HWP Team: Memory
-// *HWP Level: 2
-// *HWP Consumed by: HB:FSP
-
-#ifndef _MSS_PORT_H_
-#define _MSS_PORT_H_
-
-#include <fapi2.H>
-
-#include <p9_mc_scom_addresses.H>
-#include <p9_mc_scom_addresses_fld.H>
-
-// I have a dream that port code can be shared among controllers. So, I drive the
-// engine from a set of traits. This might be folly. Allow me to dream. BRS
-
-template< fapi2::TargetType T >
-class portTraits;
-
-// Centaur port traits
-template<>
-class portTraits<fapi2::TARGET_TYPE_MBA>
-{
-    public:
-};
-
-// Nimbus port traits
-template<>
-class portTraits<fapi2::TARGET_TYPE_MCA>
-{
-    public:
-        static const uint64_t FARB5Q_REG = MCA_MBA_FARB5Q;
-        static const uint64_t FARB0Q_REG = MCA_MBA_FARB0Q;
-        static const uint64_t REFRESH_REG = MCA_MBAREF0Q;
-        static const uint64_t ECC_REG = MCA_RECR;
-
-        enum
-        {
-            CFG_DDR_DPHY_NCLK =     MCA_MBA_FARB5Q_CFG_DDR_DPHY_NCLK,
-            CFG_DDR_DPHY_NCLK_LEN = MCA_MBA_FARB5Q_CFG_DDR_DPHY_NCLK_LEN,
-            CFG_DDR_DPHY_PCLK =     MCA_MBA_FARB5Q_CFG_DDR_DPHY_PCLK,
-            CFG_DDR_DPHY_PCLK_LEN = MCA_MBA_FARB5Q_CFG_DDR_DPHY_PCLK_LEN,
-            CFG_CCS_INST_RESET_ENABLE = MCA_MBA_FARB5Q_CFG_CCS_INST_RESET_ENABLE,
-            CFG_DDR_RESETN = MCA_MBA_FARB5Q_CFG_DDR_RESETN,
-            CFG_CCS_ADDR_MUX_SEL = MCA_MBA_FARB5Q_CFG_CCS_ADDR_MUX_SEL,
-
-            REFRESH_ENABLE = MCA_MBAREF0Q_CFG_REFRESH_ENABLE,
-
-            ECC_CHECK_DISABLE = MCA_RECR_MBSECCQ_DISABLE_MEMORY_ECC_CHECK_CORRECT,
-            ECC_CORRECT_DISABLE = MCA_RECR_MBSECCQ_DISABLE_MEMORY_ECC_CORRECT,
-
-            PORT_FAIL_DISABLE = MCA_MBA_FARB0Q_CFG_PORT_FAIL_DISABLE,
-        };
-};
-
-
-namespace mss
-{
-
-///
-/// @brief Change the state of the port_fail_disable bit
-/// @param[in] i_target the target
-/// @param[in] i_state the state
-/// @return FAPI2_RC_SUCCESS if and only if ok
-///
-template< fapi2::TargetType T, typename TT = portTraits<T> >
-fapi2::ReturnCode change_port_fail_disable( const fapi2::Target<T>& i_target, states i_state )
-{
-    fapi2::buffer<uint64_t> l_data;
-
-    FAPI_DBG("Change port fail disable to %s %s", (i_state == HIGH ? "high" : "low"), mss::c_str(i_target));
-    FAPI_TRY( mss::getScom(i_target, TT::FARB0Q_REG, l_data) );
-    l_data.writeBit<TT::PORT_FAIL_DISABLE>(i_state);
-    FAPI_TRY( mss::putScom(i_target, TT::FARB0Q_REG, l_data) );
-
-fapi_try_exit:
-    return fapi2::current_err;
-}
-
-///
-/// @brief Change the state of the addr_mux_sel bit
-/// @param[in] i_target the target
-/// @param[in] i_state the state
-/// @return FAPI2_RC_SUCCESS if and only if ok
-///
-template< fapi2::TargetType T, typename TT = portTraits<T> >
-fapi2::ReturnCode change_addr_mux_sel( const fapi2::Target<T>& i_target, states i_state )
-{
-    fapi2::buffer<uint64_t> l_data;
-
-    FAPI_DBG("Change addr_mux_sel to %s %s", (i_state == HIGH ? "high" : "low"), mss::c_str(i_target));
-    FAPI_TRY( mss::getScom(i_target, TT::FARB5Q_REG, l_data) );
-    l_data.writeBit<TT::CFG_CCS_ADDR_MUX_SEL>(i_state);
-    FAPI_TRY( mss::putScom(i_target, TT::FARB5Q_REG, l_data) );
-
-fapi_try_exit:
-    return fapi2::current_err;
-}
-
-
-///
-/// @brief Change the state of the MC Refresh enable bit
-/// @param[in] i_target the target
-/// @param[in] i_state the state
-/// @return FAPI2_RC_SUCCESS if and only if ok
-///
-template< fapi2::TargetType T, typename TT = portTraits<T> >
-fapi2::ReturnCode change_refresh_enable( const fapi2::Target<T>& i_target, states i_state )
-{
-    fapi2::buffer<uint64_t> l_data;
-
-    FAPI_DBG("Change refresh enable to %s %s", (i_state == HIGH ? "high" : "low"), mss::c_str(i_target));
-    FAPI_TRY( mss::getScom(i_target, TT::REFRESH_REG, l_data) );
-    l_data.writeBit<TT::REFRESH_ENABLE>(i_state);
-    FAPI_TRY( mss::putScom(i_target, TT::REFRESH_REG, l_data) );
-
-fapi_try_exit:
-    return fapi2::current_err;
-}
-
-///
-/// @brief Enable the MC Periodic calibration functionality
-/// @param[in] i_target the target
-/// @return FAPI2_RC_SUCCESS if and only if ok
-///
-template< fapi2::TargetType T, typename TT = portTraits<T> >
-fapi2::ReturnCode enable_periodic_cal( const fapi2::Target<T>& i_target )
-{
-    FAPI_INF("Enable periodic cal NOOP");
-    return fapi2::FAPI2_RC_SUCCESS;
-}
-
-///
-/// @brief Enable Read ECC checking
-/// @param[in] i_target the target
-/// @return FAPI2_RC_SUCCESS if and only if ok
-///
-template< fapi2::TargetType T, typename TT = portTraits<T> >
-fapi2::ReturnCode enable_read_ecc( const fapi2::Target<T>& i_target )
-{
-    fapi2::buffer<uint64_t> l_data;
-    uint8_t is_sim = 0;
-
-    FAPI_DBG("Enable Read ECC %s", mss::c_str(i_target));
-
-    FAPI_TRY( mss::getScom(i_target, TT::ECC_REG, l_data) );
-    l_data.clearBit<TT::ECC_CHECK_DISABLE>();
-    l_data.clearBit<TT::ECC_CORRECT_DISABLE>();
-
-    // The preferred operating mode is 11 (INVERT_DATA_TOGGLE_CHECKS)   which stores data complemented
-    // (because most bits are '0', and the dram bus pulls up, so transmitting 1s is least power)  but
-    // still flips the inversion of check bits to aid RAS. Per Brad Michael 12/15
-    // Leave un-inverted for sim. This allows the DIMM loader to write 0's and effect good ECC
-    FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_IS_SIMULATION, fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>(), is_sim) );
-    l_data.insertFromRight<MCA_RECR_MBSECCQ_DATA_INVERSION, MCA_RECR_MBSECCQ_DATA_INVERSION_LEN>(is_sim ? 0b00 : 0b11);
-
-    // bits: 60 MBSTRQ_CFG_MAINT_RCE_WITH_CE
-    // cfg_maint_rce_with_ce - not implemented. Need to investigate if needed for nimbus.
-
-    FAPI_TRY( mss::putScom(i_target, TT::ECC_REG, l_data) );
-
-fapi_try_exit:
-    return fapi2::current_err;
-}
-
-//
-// We expect to come in to draminit with the following setup:
-// 1. ENABLE_RESET_N (FARB5Q(6)) 0
-// 2. RESET_N (FARB5Q(4)) 1 - out of reset (done in draminit as a separate step)
-// 3. CCS_ADDR_MUX_SEL (FARB5Q(5)) - 1
-// 4. CKE out of high impedence
-// Note: Ignore resetn as it's taken care of as a separate step
-//
-///
-/// @brief Secure the entry criteria for draminit
-/// @param[in] i_target A target representing a port
-/// @return FAPI2_RC_SUCCESS if and only if ok
-// This is in this header as it's hoped to be able to be shared. Seems to make more
-// Might make more sense in p9_mss_draminit.C ... BRS
-///
-template< fapi2::TargetType T, typename TT = portTraits<T> >
-inline fapi2::ReturnCode draminit_entry_invariant( const fapi2::Target<T>& i_target )
-{
-    fapi2::buffer<uint64_t> l_data;
-    FAPI_TRY( mss::getScom(i_target, TT::FARB5Q_REG, l_data) );
-
-    if ((l_data.getBit<TT::CFG_CCS_ADDR_MUX_SEL>() != HIGH) || (l_data.getBit<TT::CFG_CCS_INST_RESET_ENABLE>() != LOW))
-    {
-        // We have some bits not set correctly. Lets try to reset the register.
-        FAPI_INF("FARB5Q: 0x%llx, setting MUX_SEL, clearing RESET_ENABLE", uint64_t(l_data));
-        l_data.setBit<TT::CFG_CCS_ADDR_MUX_SEL>();
-        l_data.clearBit<TT::CFG_CCS_INST_RESET_ENABLE>();
-        FAPI_TRY( mss::putScom(i_target, TT::FARB5Q_REG, l_data) );
-    }
-
-fapi_try_exit:
-    return fapi2::current_err;
-}
-
-///
-/// @brief Drive memory clocks
-/// @param[in] i_target A target representing a port
-/// @param[in] i_pclk phy p clock - right most 2 bits
-/// @param[in] i_nclk phy n clock - right most 2 bits
-/// @return FAPI2_RC_SUCCESS if and only if ok
-/// @note this might need a port id added for Centaur/MBA controllers
-///
-template< fapi2::TargetType T, typename TT = portTraits<T> >
-fapi2::ReturnCode drive_mem_clks( const fapi2::Target<T>& i_target, uint64_t i_pclk, uint64_t i_nclk )
-{
-    fapi2::buffer<uint64_t> l_data;
-
-    FAPI_DBG("Drive mem clocks");
-    FAPI_TRY( mss::getScom(i_target, TT::FARB5Q_REG, l_data) );
-
-    l_data.insertFromRight<TT::CFG_DDR_DPHY_NCLK, TT::CFG_DDR_DPHY_NCLK_LEN>(i_nclk);
-    l_data.insertFromRight<TT::CFG_DDR_DPHY_PCLK, TT::CFG_DDR_DPHY_PCLK_LEN>(i_pclk);
-
-    FAPI_TRY( mss::putScom(i_target, TT::FARB5Q_REG, l_data) );
-
-    return fapi2::FAPI2_RC_SUCCESS;
-
-fapi_try_exit:
-    FAPI_ERR("Unable to drive mem clocks: %s", mss::c_str(i_target));
-    return fapi2::current_err;
-}
-
-///
-/// @brief Set DDR resetn
-/// @param[in] i_target A target representing a port
-/// @param[in] i_state high or low
-/// @return FAPI2_RC_SUCCESS if and only if ok
-/// @note this might need a port id added for Centaur/MBA controllers
-///
-template< fapi2::TargetType T, typename TT = portTraits<T> >
-fapi2::ReturnCode ddr_resetn( const fapi2::Target<T>& i_target, bool i_state )
-{
-    fapi2::buffer<uint64_t> l_data;
-    FAPI_TRY( mss::getScom(i_target, TT::FARB5Q_REG, l_data) );
-
-    if (l_data.getBit<TT::CFG_DDR_RESETN>() != i_state)
-    {
-        l_data.writeBit<TT::CFG_DDR_RESETN>(i_state);
-        FAPI_DBG("ddr_resetn transitioning to %d (0x%llx)", i_state, l_data);
-        FAPI_TRY( mss::putScom(i_target, TT::FARB5Q_REG, l_data) );
-    }
-
-    return fapi2::FAPI2_RC_SUCCESS;
-
-fapi_try_exit:
-    FAPI_ERR("Unable to change resetn: %s (%d)", mss::c_str(i_target), i_state);
-    return fapi2::current_err;
-}
-
-}
-#endif
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/shared/mss_const.H b/src/import/chips/p9/procedures/hwp/memory/lib/shared/mss_const.H
index 668a2373e..5a9a53037 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/shared/mss_const.H
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/shared/mss_const.H
@@ -38,6 +38,8 @@ enum sizes
 {
     PORTS_PER_MCS = 2,
     PORTS_PER_MCBIST = 4,
+    MC_PER_MODULE = 2,
+    MCBIST_PER_MC = 1,
     MAX_DIMM_PER_PORT = 2,
     MAX_RANK_PER_DIMM = 4,
     RANK_MID_POINT = 4,            ///< Which rank number indicates the switch to the other DIMM
diff --git a/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit_mc.C b/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit_mc.C
index dd406966e..27f645360 100644
--- a/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit_mc.C
+++ b/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit_mc.C
@@ -86,6 +86,11 @@ extern "C"
             // Re-enable port fails. Turned off in draminit_training
             FAPI_TRY( mss::change_port_fail_disable(p, mss::OFF ) );
 
+            // MC work around for OE bug (seen in periodics + PHY)
+#ifndef REMOVE_FOR_DD2
+            // Turn on output-enable always on. Shelton tells me they'll fix for DD2
+            FAPI_TRY( mss::change_oe_always_on(p, mss::ON ) );
+#endif
             // Step Two.1: Check RCD protect time on RDIMM and LRDIMM
             // Step Two.2: Enable address inversion on each MBA for ALL CARDS