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authorLouis Stermole <stermole@us.ibm.com>2018-10-12 08:58:56 -0500
committerChristian R. Geddes <crgeddes@us.ibm.com>2019-02-19 09:21:09 -0600
commit1fba0b5d505f374794ad1428ea8ba7a8b299adab (patch)
treeecf7004f758757ae57f2c7e89a3182067bcc56f0 /src/import/chips/p9a
parentc20c2b87a3bda79ceaf821f3b2a6e3ab8477358b (diff)
downloadtalos-hostboot-1fba0b5d505f374794ad1428ea8ba7a8b299adab.tar.gz
talos-hostboot-1fba0b5d505f374794ad1428ea8ba7a8b299adab.zip
Add p9a_mss_volt procedure
Change-Id: Ibcbfc4fbd78beb2a4793f15dcc61a3d1ff5cf679 Original-Change-Id: I893685b365f6c815653717d4cc8149f2ea7acb94 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/68412 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: STEPHEN GLANCY <sglancy@us.ibm.com> Reviewed-by: ANDRE A. MARIN <aamarin@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/72089 Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>
Diffstat (limited to 'src/import/chips/p9a')
-rw-r--r--src/import/chips/p9a/procedures/hwp/memory/lib/eff_config/axone_mss_voltage.C95
-rw-r--r--src/import/chips/p9a/procedures/hwp/memory/p9a_mss_freq_system.H1
2 files changed, 95 insertions, 1 deletions
diff --git a/src/import/chips/p9a/procedures/hwp/memory/lib/eff_config/axone_mss_voltage.C b/src/import/chips/p9a/procedures/hwp/memory/lib/eff_config/axone_mss_voltage.C
index 2fc10aad8..27a815421 100644
--- a/src/import/chips/p9a/procedures/hwp/memory/lib/eff_config/axone_mss_voltage.C
+++ b/src/import/chips/p9a/procedures/hwp/memory/lib/eff_config/axone_mss_voltage.C
@@ -22,3 +22,98 @@
/* permissions and limitations under the License. */
/* */
/* IBM_PROLOG_END_TAG */
+
+///
+/// @file axone_mss_voltage.C
+/// @brief Axone specializations for voltage library
+///
+// *HWP HWP Owner: Louis Stermole <stermole@us.ibm.com>
+// *HWP HWP Backup: Stephen Glancy <sglancy@us.ibm.com>
+// *HWP Team: Memory
+// *HWP Level: 3
+// *HWP Consumed by: HB:FSP
+
+#include <fapi2.H>
+#include <vector>
+
+// Memory libraries
+#include <exp_attribute_accessors_manual.H>
+
+// Generic libraries
+#include <generic/memory/lib/utils/shared/mss_generic_consts.H>
+#include <generic/memory/lib/utils/find.H>
+#include <generic/memory/lib/spd/spd_facade.H>
+#include <generic/memory/lib/utils/voltage/gen_mss_voltage_traits.H>
+#include <generic/memory/lib/utils/voltage/gen_mss_volt.H>
+
+namespace mss
+{
+
+using TT = mss::voltage_traits<mss::mc_type::EXPLORER, mss::spd::device_type::DDR4>;
+
+// List of attribute setter functions for setting voltage rail values
+const std::vector<fapi2::ReturnCode (*)(const fapi2::Target<TT::VOLTAGE_TARGET_TYPE>&, uint32_t)>
+TT::voltage_setters =
+{
+ &set_volt_vddr,
+ &set_volt_vpp,
+};
+
+///
+/// @brief Determine what voltages are supported for the given memory controller and DRAM generation
+/// @param[in] i_target the target for setting voltage attributes
+/// @param[out] o_supported_dram_voltages vector of supported rail voltages in millivolts to be used in set_voltage_attributes
+/// @return FAPI2_RC_SUCCESS iff ok
+/// @note AXONE, DDR4 specialization
+///
+template<>
+fapi2::ReturnCode get_supported_voltages<mss::mc_type::EXPLORER, mss::spd::device_type::DDR4>
+(const fapi2::Target<TT::SPD_TARGET_TYPE>& i_target,
+ std::vector<uint32_t>& o_supported_dram_voltages)
+{
+ o_supported_dram_voltages.clear();
+
+ FAPI_INF("Populating decoder cache for %s", mss::c_str(i_target));
+
+ // Factory cache is per port
+ std::vector< mss::spd::facade > l_spd_facades;
+ FAPI_TRY( get_spd_decoder_list(i_target, l_spd_facades), "%s Failed to get SPD decoder list", mss::c_str(i_target) );
+
+ // Get DIMM for each port
+ for ( const auto& l_cache : l_spd_facades )
+ {
+ const auto l_dimm = l_cache.get_dimm_target();
+ uint8_t l_dimm_nominal = 0;
+ uint8_t l_dimm_endurant = 0;
+
+ // Read nominal and endurant bits from SPD, 0 = 1.2V is not operable and endurant, 1 = 1.2 is valid
+ FAPI_TRY( l_cache.operable_nominal_voltage(l_dimm_nominal) );
+ FAPI_TRY( l_cache.endurant_nominal_voltage(l_dimm_endurant) );
+
+ //Check to make sure 1.2 V is both operable and endurant, fail if it is not
+ FAPI_ASSERT ( (l_dimm_nominal == mss::spd::OPERABLE) && (l_dimm_endurant == mss::spd::ENDURANT),
+ fapi2::MSS_VOLT_DDR_TYPE_REQUIRED_VOLTAGE().
+ set_ACTUAL_OPERABLE(l_dimm_nominal).
+ set_ACTUAL_ENDURANT(l_dimm_endurant).
+ set_EXPECTED_OPERABLE(mss::spd::OPERABLE).
+ set_EXPECTED_ENDURANT(mss::spd::ENDURANT).
+ set_DIMM_TARGET(l_dimm),
+ "%s: DIMM is not operable (%d) expected (%d)"
+ " and/or endurant (%d) expected (%d) at 1.2V",
+ mss::c_str(l_dimm),
+ l_dimm_nominal,
+ mss::spd::OPERABLE,
+ l_dimm_endurant,
+ mss::spd::ENDURANT);
+ } // l_dimm
+
+ // Set the attributes for this port, values are in mss_const.H
+ // The ordering of voltages is specified in the selected voltage_traits specialization
+ o_supported_dram_voltages.push_back(TT::DDR4_NOMINAL_VOLTAGE);
+ o_supported_dram_voltages.push_back(TT::DDR4_VPP_VOLTAGE);
+
+fapi_try_exit:
+ return fapi2::current_err;
+}
+
+} // ns mss
diff --git a/src/import/chips/p9a/procedures/hwp/memory/p9a_mss_freq_system.H b/src/import/chips/p9a/procedures/hwp/memory/p9a_mss_freq_system.H
index 11d6230fd..cbf2d718c 100644
--- a/src/import/chips/p9a/procedures/hwp/memory/p9a_mss_freq_system.H
+++ b/src/import/chips/p9a/procedures/hwp/memory/p9a_mss_freq_system.H
@@ -50,7 +50,6 @@ extern "C"
/// @return FAPI2_RC_SUCCESS iff ok
///
fapi2::ReturnCode p9a_mss_freq_system(const fapi2::Target<fapi2::TARGET_TYPE_MC>& i_target);
-
}
#endif
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