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author | Devon Baughen <devon.baughen1@ibm.com> | 2019-06-14 15:55:50 -0500 |
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committer | Christian R. Geddes <crgeddes@us.ibm.com> | 2019-06-25 09:20:59 -0500 |
commit | 04a0314a1b44d4bbb39257e3829bb47e6aa0166b (patch) | |
tree | 6f05a3b6d5aa71421d859099701af1ee45c54003 /src/import/chips/p9a/procedures/hwp/memory/lib/mc/omi.H | |
parent | d58f3a70853561086ed2d2b128a758004cc575cb (diff) | |
download | talos-hostboot-04a0314a1b44d4bbb39257e3829bb47e6aa0166b.tar.gz talos-hostboot-04a0314a1b44d4bbb39257e3829bb47e6aa0166b.zip |
add manual omi training sequence
Change-Id: I76979bacddd8054d6935651d67051bf515a330c5
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/78986
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: STEPHEN GLANCY <sglancy@us.ibm.com>
Reviewed-by: Mark Pizzutillo <mark.pizzutillo@ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Jennifer A Stofer <stofer@us.ibm.com>
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/79126
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>
Diffstat (limited to 'src/import/chips/p9a/procedures/hwp/memory/lib/mc/omi.H')
-rw-r--r-- | src/import/chips/p9a/procedures/hwp/memory/lib/mc/omi.H | 9 |
1 files changed, 5 insertions, 4 deletions
diff --git a/src/import/chips/p9a/procedures/hwp/memory/lib/mc/omi.H b/src/import/chips/p9a/procedures/hwp/memory/lib/mc/omi.H index f7a9f08b3..06471052e 100644 --- a/src/import/chips/p9a/procedures/hwp/memory/lib/mc/omi.H +++ b/src/import/chips/p9a/procedures/hwp/memory/lib/mc/omi.H @@ -470,10 +470,11 @@ fapi_try_exit: /// @tparam T the fapi2 target type of the target /// @tparam TT the class traits for the omi /// @param[in] i_target the OMI target to operate on +/// @param[in] i_train_mode training step to enable /// @return FAPI2_RC_SUCCESS iff ok /// template< mss::proc_type PROC = DEFAULT_PROC_TYPE, fapi2::TargetType T, typename TT = omiTraits<T, PROC>> -fapi2::ReturnCode setup_mc_config0_helper(const fapi2::Target<T>& i_target) +fapi2::ReturnCode setup_mc_config0_helper(const fapi2::Target<T>& i_target, const uint8_t i_train_mode) { // The value is 0x8200040000152824 fapi2::buffer<uint64_t> l_val; @@ -576,7 +577,7 @@ fapi2::ReturnCode setup_mc_config0_helper(const fapi2::Target<T>& i_target) // CFG_DL0_TRAIN_MODE: dl0 train mode l_val.template insertFromRight<TT::MC_REG2_DL0_CONFIG0_CFG_TRAIN_MODE, TT::MC_REG2_DL0_CONFIG0_CFG_TRAIN_MODE_LEN> - (ENABLE_AUTO_TRAINING); + (i_train_mode); // CFG_DL0_VERSION: dl0 version number l_val.template insertFromRight<TT::MC_REG2_DL0_CONFIG0_CFG_VERSION, TT::MC_REG2_DL0_CONFIG0_CFG_VERSION_LEN>(9); @@ -614,8 +615,8 @@ fapi2::ReturnCode setup_mc_config1_helper(const fapi2::Target<T>& i_target) // CFG_DL0_CFG1_PREIPL_PRBS l_val.template insertFromRight<TT::MC_REG2_DL0_CONFIG1_CFG_PREIPL_PRBS_TIME, TT::MC_REG2_DL0_CONFIG1_CFG_PREIPL_PRBS_TIME_LEN>(l_sim ? PREIPL_PRBS_1US : PREIPL_PRBS_256MS); - - l_val.template writeBit<TT::MC_REG2_DL0_CONFIG1_CFG_PREIPL_PRBS_ENA, 1>(1); // Enable + // PRE-IPL PRBS Timing is not functional in Axone, so set to disable + l_val.template writeBit<TT::MC_REG2_DL0_CONFIG1_CFG_PREIPL_PRBS_ENA, 1>(0); // Disable l_val.template insertFromRight<TT::MC_REG2_DL0_CONFIG1_CFG_LANE_WIDTH, TT::MC_REG2_DL0_CONFIG1_CFG_LANE_WIDTH_LEN>(TL_CTR_BY_SIDEBAND); |