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author | Greg Still <stillgs@us.ibm.com> | 2018-06-19 22:36:10 -0500 |
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committer | Daniel M. Crowell <dcrowell@us.ibm.com> | 2018-06-25 10:57:40 -0400 |
commit | e95497ee0e43afa23b012ff4b1c400ef0dc0ace7 (patch) | |
tree | 75dc445eb4b6c0894a176da6b32a22df448b3bc2 /src/import/chips/p9 | |
parent | 4d9e273baf30938c2b8eadeae5fdd4faf0ab2bd3 (diff) | |
download | talos-hostboot-e95497ee0e43afa23b012ff4b1c400ef0dc0ace7.tar.gz talos-hostboot-e95497ee0e43afa23b012ff4b1c400ef0dc0ace7.zip |
PM: Fix double biases value into safe mode frequency
- Removed the in-place biasing of the VPD operating point structure that led
to compounding when non-zero.
Key_Cronus_Test=PM_REGRESS
Change-Id: I5108cd633a849a292d1eef3aee5fef22c5cef62f
CQ: SW434117
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/60932
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/60933
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Diffstat (limited to 'src/import/chips/p9')
-rw-r--r-- | src/import/chips/p9/procedures/hwp/pm/p9_setup_evid.C | 25 |
1 files changed, 19 insertions, 6 deletions
diff --git a/src/import/chips/p9/procedures/hwp/pm/p9_setup_evid.C b/src/import/chips/p9/procedures/hwp/pm/p9_setup_evid.C index d52409657..f18c220a2 100644 --- a/src/import/chips/p9/procedures/hwp/pm/p9_setup_evid.C +++ b/src/import/chips/p9/procedures/hwp/pm/p9_setup_evid.C @@ -111,6 +111,7 @@ compute_boot_safe(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target, fapi2::ReturnCode l_rc; uint32_t attr_mvpd_poundv[PV_D][PV_W]; + uint32_t attr_mvpd_poundv_biased[PV_D][PV_W]; uint32_t valid_pdv_points; uint8_t present_chiplets; @@ -173,8 +174,21 @@ compute_boot_safe(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target, attrs->proc_dpll_divider = 8; } + FAPI_DBG("Copy to Bias array"); + + for (int i = 0; i < NUM_OP_POINTS; i++) + { + for (int d = 0; d < PV_D; ++d) + { + for (int w = 0; w < PV_W; ++w) + { + attr_mvpd_poundv_biased[d][w] = attr_mvpd_poundv[d][w]; + } + } + } + // Apply Bias values - FAPI_TRY(proc_get_extint_bias(attr_mvpd_poundv, + FAPI_TRY(proc_get_extint_bias(attr_mvpd_poundv_biased, attrs, l_vpdbias), "Bias application function failed"); @@ -255,13 +269,12 @@ compute_boot_safe(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target, else { FAPI_INF("VCS boot voltage override not set, using VPD value and correcting for applicable load line setting"); - uint32_t l_int_vcs_mv = (attr_mvpd_poundv[POWERSAVE][VPD_PV_VCS_MV]); - uint32_t l_ics_ma = (attr_mvpd_poundv[POWERSAVE][VPD_PV_ICS_100MA]) * 100; + uint32_t l_int_vcs_mv = (attr_mvpd_poundv_biased[POWERSAVE][VPD_PV_VCS_MV]); + uint32_t l_ics_ma = (attr_mvpd_poundv_biased[POWERSAVE][VPD_PV_ICS_100MA]) * 100; uint32_t l_ext_vcs_mv = sysparm_uplift(l_int_vcs_mv, l_ics_ma, attrs->r_loadline_vcs_uohm, - attrs->r_distloss_vcs_uohm, attrs->vrm_voffset_vcs_uv); @@ -287,8 +300,8 @@ compute_boot_safe(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target, else { FAPI_INF("VDN boot voltage override not set, using VPD value and correcting for applicable load line setting"); - uint32_t l_int_vdn_mv = (attr_mvpd_poundv[POWERBUS][VPD_PV_VDN_MV]); - uint32_t l_idn_ma = (attr_mvpd_poundv[POWERBUS][VPD_PV_IDN_100MA]) * 100; + uint32_t l_int_vdn_mv = (attr_mvpd_poundv_biased[POWERBUS][VPD_PV_VDN_MV]); + uint32_t l_idn_ma = (attr_mvpd_poundv_biased[POWERBUS][VPD_PV_IDN_100MA]) * 100; // Returns revle32 uint32_t l_ext_vdn_mv = sysparm_uplift(l_int_vdn_mv, l_idn_ma, |