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| author | Thi Tran <thi@us.ibm.com> | 2017-04-28 07:23:14 -0500 |
|---|---|---|
| committer | Daniel M. Crowell <dcrowell@us.ibm.com> | 2017-05-03 13:19:52 -0400 |
| commit | 2ca7c69626ad6025bfcbe452f6b7e911327de58d (patch) | |
| tree | 1e4220e0303801d414afe71cd9d68b7082a2515d /src/import/chips/p9 | |
| parent | a258ae0062275881db2d0c29511e609a1a1ce514 (diff) | |
| download | talos-hostboot-2ca7c69626ad6025bfcbe452f6b7e911327de58d.tar.gz talos-hostboot-2ca7c69626ad6025bfcbe452f6b7e911327de58d.zip | |
p9_mss_eff_grouping - Fix memory hole start/end addresses
The memory hole addresses need to be set as absolute
addresses (currently set as group local address).
Change-Id: Ieb5da460a4fb717424732539c09232e87572ddd5
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/39804
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
Reviewed-by: Benjamin Gass <bgass@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/39806
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Diffstat (limited to 'src/import/chips/p9')
| -rw-r--r-- | src/import/chips/p9/procedures/hwp/nest/p9_mss_eff_grouping.C | 51 |
1 files changed, 21 insertions, 30 deletions
diff --git a/src/import/chips/p9/procedures/hwp/nest/p9_mss_eff_grouping.C b/src/import/chips/p9/procedures/hwp/nest/p9_mss_eff_grouping.C index 60f26f3c8..34f7e55f5 100644 --- a/src/import/chips/p9/procedures/hwp/nest/p9_mss_eff_grouping.C +++ b/src/import/chips/p9/procedures/hwp/nest/p9_mss_eff_grouping.C @@ -2522,23 +2522,23 @@ fapi2::ReturnCode grouping_calcMirrorMemory( // The 2nd memory hole was intended for use with 12Gb DRAM parts, // which we do not have to support - so it will not be used in Nimbus. io_groupData.iv_data[pos][BASE_ADDR] = memBaseAddr_GB; - - if (io_groupData.iv_data[pos][ALT_VALID(0)]) - { - io_groupData.iv_data[pos][ALT_BASE_ADDR(0)] = io_groupData.iv_data[pos][BASE_ADDR] + - (io_groupData.iv_data[pos][GROUP_SIZE] / 2); - } } else { - io_groupData.iv_data[pos][BASE_ADDR] = io_groupData.iv_data[pos - 1][BASE_ADDR] + - io_groupData.iv_data[pos - 1][GROUP_SIZE]; + io_groupData.iv_data[pos][BASE_ADDR] = + io_groupData.iv_data[pos - 1][BASE_ADDR] + + io_groupData.iv_data[pos - 1][GROUP_SIZE]; + } - if (io_groupData.iv_data[pos][ALT_VALID(0)]) - { - io_groupData.iv_data[pos][ALT_BASE_ADDR(0)] = io_groupData.iv_data[pos][BASE_ADDR] + - io_groupData.iv_data[pos][GROUP_SIZE] / 2; - } + // Note: + // The 2nd memory hole was intended for use with 12Gb DRAM parts, + // which we do not have to support - so it will not be used in Nimbus. + if (io_groupData.iv_data[pos][ALT_VALID(0)]) + { + io_groupData.iv_data[pos][ALT_BASE_ADDR(0)] = + io_groupData.iv_data[pos][BASE_ADDR] + + io_groupData.iv_data[pos][GROUP_SIZE] - + io_groupData.iv_data[pos][ALT_SIZE(0)]; } if (io_groupData.iv_data[pos][PORTS_IN_GROUP] > 1) @@ -2598,31 +2598,22 @@ void grouping_calcNonMirrorMemory(const EffGroupingProcAttrs& i_procAttrs, { io_groupData.iv_data[pos][BASE_ADDR] = (i_procAttrs.iv_memBaseAddr >> 30); - - for (uint8_t ii = 0; ii < NUM_OF_ALT_MEM_REGIONS; ii++) - { - if (io_groupData.iv_data[pos][ALT_VALID(ii)]) - { - io_groupData.iv_data[pos][ALT_BASE_ADDR(ii)] = - io_groupData.iv_data[pos][GROUP_SIZE] - - io_groupData.iv_data[pos][ALT_SIZE(ii)]; - } - } } else { io_groupData.iv_data[pos][BASE_ADDR] = io_groupData.iv_data[pos - 1][BASE_ADDR] + io_groupData.iv_data[pos - 1][GROUP_SIZE]; + } - for (uint8_t ii = 0; ii < NUM_OF_ALT_MEM_REGIONS; ii++) + for (uint8_t ii = 0; ii < NUM_OF_ALT_MEM_REGIONS; ii++) + { + if (io_groupData.iv_data[pos][ALT_VALID(ii)]) { - if (io_groupData.iv_data[pos][ALT_VALID(ii)]) - { - io_groupData.iv_data[pos][ALT_BASE_ADDR(ii)] = - io_groupData.iv_data[pos][GROUP_SIZE] - - io_groupData.iv_data[pos][ALT_SIZE(ii)]; - } + io_groupData.iv_data[pos][ALT_BASE_ADDR(ii)] = + io_groupData.iv_data[pos][BASE_ADDR] + + io_groupData.iv_data[pos][GROUP_SIZE] - + io_groupData.iv_data[pos][ALT_SIZE(ii)]; } } } |
