Adds per-Buffer addressability API for LRDIMM

Change-Id: I600dd1fe8b9595d2bc0041e7fc2c009c2477d0e3
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/66727
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Louis Stermole <stermole@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/66759
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>

9 files changed, 104 insertions, 57 deletions

diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/ccs/ccs.H b/src/import/chips/p9/procedures/hwp/memory/lib/ccs/ccs.H
index 55454b53d..f63aafc4d 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/ccs/ccs.H
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/ccs/ccs.H
@@ -27,7 +27,7 @@
 /// @file ccs.H
 /// @brief Run and manage the CCS engine
 ///
-// *HWP HWP Owner: Jacob Harvey <jlharvey@us.ibm.com>
+// *HWP HWP Owner: Stephen Glancy <sglancy@us.ibm.com>
 // *HWP HWP Backup: Andre Marin <aamarin@us.ibm.com>
 // *HWP Team: Memory
 // *HWP Level: 3
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/bcw_load_ddr4.C b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/bcw_load_ddr4.C
index 0e0e10a6a..7c8af9313 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/bcw_load_ddr4.C
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/bcw_load_ddr4.C
@@ -28,7 +28,7 @@
 /// @brief Run and manage the DDR4 bcw loading
 ///
 // *HWP HWP Owner: Andre Marin <aamarin@us.ibm.com>
-// *HWP HWP Backup: Jacob Harvey <jlharvey@us.ibm.com>
+// *HWP HWP Backup: Stephen Glancy <sglancy@us.ibm.com>
 // *HWP Team: Memory
 // *HWP Level: 3
 // *HWP Consumed by: FSP:HB
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/control_word_ddr4.H b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/control_word_ddr4.H
index bbef1f8c9..5dae509a6 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/control_word_ddr4.H
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/control_word_ddr4.H
@@ -28,7 +28,7 @@
 /// @brief Run and manage the DDR4 control words for the RCD and data buffers
 ///
 // *HWP HWP Owner: Andre Marin <aamarin@us.ibm.com>
-// *HWP HWP Backup: Jacob Harvey <jlharvey@us.ibm.com>
+// *HWP HWP Backup: Stephen Glancy <sglancy@us.ibm.com>
 // *HWP Team: Memory
 // *HWP Level: 3
 // *HWP Consumed by: FSP:HB
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/data_buffer_ddr4.H b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/data_buffer_ddr4.H
index db26abc36..055757b19 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/data_buffer_ddr4.H
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/data_buffer_ddr4.H
@@ -28,7 +28,7 @@
 /// @brief Code to support data_buffer_ddr4
 ///
 // *HWP HWP Owner: Andre Marin <aamarin@us.ibm.com>
-// *HWP HWP Backup: Jacob Harvey <jlharvey@us.ibm.com>
+// *HWP HWP Backup: Stephen Glancy <sglancy@us.ibm.com>
 // *HWP Team: Memory
 // *HWP Level: 3
 // *HWP Consumed by: HB:FSP
@@ -48,11 +48,6 @@
 namespace mss
 {
 // TK:LRDIMM Verify this functionality and data (looked good to me, but more eyes are better - SPG)
-// TK:LRDIMM Create automatic function space selector code
-// The idea behind this is
-// 1) function space 0 is the default
-// 2) we want to be able to say "here's a bunch of buffer control words, hit the appropriate function space before each is needed)
-// Will greatly simplify code
 
 enum nibble : size_t
 {
@@ -74,7 +69,7 @@ enum db02_def : size_t
     FUNC_SPACE_7 = 7,
 
     // From DB02 spec - F[3:0]BC7x control word
-    MAX_FUNC_SPACE = 7,
+    MAX_FUNC_SPACE = FUNC_SPACE_7,
 
     // 4 bit BCWs
     DQ_RTT_NOM_CW = 0x0,
@@ -249,6 +244,9 @@ static fapi2::ReturnCode settings_boilerplate(const fapi2::Target< fapi2::TARGET
     uint8_t l_sim = 0;
     mss::is_simulation(l_sim);
 
+    // DES first - make sure those CKE go high and stay there
+    io_inst.push_back(mss::ccs::des_command<fapi2::TARGET_TYPE_MCBIST>());
+
     FAPI_TRY( function_space_select(i_target, i_data.iv_func_space, io_inst),
               "%s. Failed to select function space %d",
               mss::c_str(i_target), uint8_t(i_data.iv_func_space) );
@@ -484,13 +482,14 @@ inline fapi2::ReturnCode set_pba_mode( const fapi2::Target<fapi2::TARGET_TYPE_DI
     }
 
     cw_data l_data(FUNC_SPACE_0, BUFF_CONFIG_CW, i_state, mss::tmrc());
+    FAPI_INF("%s data 0x%02x", mss::c_str(i_target), l_data.iv_data);
     FAPI_TRY( settings_boilerplate<BCW_8BIT>(i_target, l_data, io_inst) );
 
 fapi_try_exit:
     return fapi2::current_err;
 }
 
-}// namespace ddr4
+} // namespace ddr4
 } // namespace mss
 
 #endif
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/pda.C b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/pda.C
index b7f5e475a..2f22c42a0 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/pda.C
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/pda.C
@@ -101,43 +101,6 @@ const std::vector<std::pair<uint64_t, uint64_t>> pdaBitTraits<fapi2::ENUM_ATTR_E
 };
 
 ///
-/// @brief Helper function for changing the DRAM bit
-/// @tparam W the DRAM width
-/// @tparam TT the DRAM width traits class
-/// @param[in] i_target - the MCA target
-/// @param[in] i_dram - the DRAM on which to operate
-/// @param[in] i_state - the state to write the bit(s) to
-/// @return FAPI2_RC_SUCCESS if and only if ok
-///
-template< uint8_t W, typename TT = pdaBitTraits<W> >
-fapi2::ReturnCode change_dram_bit_helper( const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target,
-        const uint64_t i_dram,
-        const mss::states& i_state)
-{
-    fapi2::buffer<uint64_t> l_data;
-
-    // Note: the following avoids "undefined reference to" errors due to the set max dram below
-    // The use of traits and a const reference messes with it
-    constexpr auto NUM_DRAM = TT::NUM_DRAMS;
-
-    // Check bounds
-    FAPI_ASSERT(i_dram < NUM_DRAM,
-                fapi2::MSS_PDA_DRAM_OUT_OF_RANGE().
-                set_MCA_TARGET(i_target).
-                set_DRAM(i_dram).
-                set_MAX_DRAM(NUM_DRAM),
-                "%s was passed DRAM value of %lu which is not below the max value of %lu",
-                mss::c_str(i_target), i_dram, NUM_DRAM);
-
-    FAPI_TRY(mss::getScom(i_target, TT::BIT_MAP[i_dram].first, l_data));
-    FAPI_TRY(l_data.writeBit(i_state, TT::BIT_MAP[i_dram].second, TT::NUM_BITS));
-    FAPI_TRY(mss::putScom(i_target, TT::BIT_MAP[i_dram].first, l_data));
-
-fapi_try_exit:
-    return fapi2::current_err;
-}
-
-///
 /// @brief Writes the data bit enable for the properly inputted DRAM
 /// @param[in] i_target - the MCA target
 /// @param[in] i_dram - the DRAM on which to operate
@@ -216,7 +179,7 @@ fapi_try_exit:
 /// @param[in] i_target a fapi2::Target MCA
 /// @return FAPI2_RC_SUCCESS if and only if ok
 ///
-fapi2::ReturnCode configure_timings( const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target )
+fapi2::ReturnCode configure_timings_and_enable( const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target )
 {
     // Fun fact, we're hitting all of the bits in this reg, no need for RMW
     fapi2::buffer<uint64_t> l_data;
@@ -226,8 +189,7 @@ fapi2::ReturnCode configure_timings( const fapi2::Target<fapi2::TARGET_TYPE_MCA>
     // 2) Have a 0 delay between the MRS being sent and starting the 0/1 latching
     // 3) Hold the delay for as long as possible (safer and easier than figuring out how long to hold the values)
     mss::wc::set_pda_mode(l_data, mss::states::ON);
-    mss::wc::set_pda_dq_on_delay(l_data, START_DELAY_VALUE);
-    mss::wc::set_pda_dq_off_delay(l_data, HOLD_DELAY_VALUE);
+    configure_timings(l_data);
 
     // Set that reg
     FAPI_TRY(mss::wc::write_config3(i_target, l_data));
@@ -282,7 +244,7 @@ fapi2::ReturnCode enter( const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
               i_rank, mss::c_str(i_target) );
 
     // Now sets up all of the PDA regs now that we are in PDA mode
-    FAPI_TRY(configure_timings(l_mca));
+    FAPI_TRY(configure_timings_and_enable(l_mca));
     FAPI_TRY(blast_dram_config(l_mca, mss::states::OFF_N));
 
 fapi_try_exit:
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/pda.H b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/pda.H
index ae622e389..379b0a2ba 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/pda.H
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/pda.H
@@ -131,10 +131,25 @@ inline void set_dram_enable( fapi2::buffer<uint64_t>& io_data, const mss::states
 
 ///
 /// @brief Configures PDA timings
+/// @param[in,out] io_buffer buffer on which the PDA timings live
+/// @note Configuring timings is a helper function, as it is used both in PDA and PBA
+/// PBA requires that we set the timings, but not enable PDA mode in the WC config, so we have a helper function
+///
+inline void configure_timings( fapi2::buffer<uint64_t>& io_buffer )
+{
+    // So we want to:
+    // Have a 0 delay between the MRS being sent and starting the 0/1 latching
+    mss::wc::set_pda_dq_on_delay(io_buffer, START_DELAY_VALUE);
+    // Hold the delay for as long as possible (safer and easier than figuring out how long to hold the values)
+    mss::wc::set_pda_dq_off_delay(io_buffer, HOLD_DELAY_VALUE);
+}
+
+///
+/// @brief Configures PDA timings
 /// @param[in] i_target a fapi2::Target MCA
 /// @return FAPI2_RC_SUCCESS if and only if ok
 ///
-fapi2::ReturnCode configure_timings( const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target );
+fapi2::ReturnCode configure_timings_and_enable( const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target );
 
 ///
 /// @brief Configures all DRAM level configuration bits to the inputted settings
@@ -187,11 +202,47 @@ fapi2::ReturnCode exit( const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
                         const uint64_t i_rank );
 
 ///
+/// @brief Helper function for changing the DRAM bit
+/// @tparam W the DRAM width
+/// @tparam TT the DRAM width traits class
+/// @param[in] i_target - the MCA target
+/// @param[in] i_dram - the DRAM on which to operate
+/// @param[in] i_state - the state to write the bit(s) to
+/// @return FAPI2_RC_SUCCESS if and only if ok
+///
+template< uint8_t W, typename TT = pdaBitTraits<W> >
+fapi2::ReturnCode change_dram_bit_helper( const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target,
+        const uint64_t i_dram,
+        const mss::states& i_state)
+{
+    fapi2::buffer<uint64_t> l_data;
+
+    // Note: the following avoids "undefined reference to" errors due to the set max dram below
+    // The use of traits and a const reference messes with it
+    constexpr auto NUM_DRAM = TT::NUM_DRAMS;
+
+    // Check bounds
+    FAPI_ASSERT(i_dram < NUM_DRAM,
+                fapi2::MSS_PDA_DRAM_OUT_OF_RANGE().
+                set_MCA_TARGET(i_target).
+                set_DRAM(i_dram).
+                set_MAX_DRAM(NUM_DRAM),
+                "%s was passed DRAM value of %lu which is not below the max value of %lu",
+                mss::c_str(i_target), i_dram, NUM_DRAM);
+
+    FAPI_TRY(mss::getScom(i_target, TT::BIT_MAP[i_dram].first, l_data));
+    FAPI_TRY(l_data.writeBit(i_state, TT::BIT_MAP[i_dram].second, TT::NUM_BITS));
+    FAPI_TRY(mss::putScom(i_target, TT::BIT_MAP[i_dram].first, l_data));
+
+fapi_try_exit:
+    return fapi2::current_err;
+}
+
+///
 /// @brief Writes the data bit enable for the properly inputted DRAM
 /// @param[in] i_target - the MCA target
 /// @param[in] i_dram - the DRAM on which to operate
 /// @param[in] i_state - the state to write the bit(s) to
-/// @param[in] i_delay the delay to use for the PDA command
 /// @note PDA is LOW enable, so 0's means ON. ON will configure the register to 0's
 ///
 fapi2::ReturnCode change_dram_bit( const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target,
@@ -303,7 +354,6 @@ class commands
     private:
         // The following is a map of target/DIMM pairs as the key to a map of
         // the MRS command as the key to the DRAM's to toggle. An explanation as to the data structure is included below
-        // Note: due to HB compile, a vector is used instead of a map
 
         // PDA compression is a little complex, but is organized to allow us to minimize the number of commands run
         // Each individual map is designed to further minimize the number of commands run
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/phy/phy_cntrl.H b/src/import/chips/p9/procedures/hwp/memory/lib/phy/phy_cntrl.H
index dc28b12c1..575d92db6 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/phy/phy_cntrl.H
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/phy/phy_cntrl.H
@@ -5,7 +5,7 @@
 /*                                                                        */
 /* OpenPOWER HostBoot Project                                             */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2016,2017                        */
+/* Contributors Listed Below - COPYRIGHT 2016,2018                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
 /*                                                                        */
@@ -39,6 +39,7 @@
 #include <fapi2.H>
 #include <p9_mc_scom_addresses.H>
 #include <p9_mc_scom_addresses_fld.H>
+#include <p9n2_mc_scom_addresses_fld.H>
 
 #include <lib/shared/mss_const.H>
 #include <generic/memory/lib/utils/scom.H>
@@ -156,6 +157,7 @@ class pcTraits<fapi2::TARGET_TYPE_MCA>
             DDR4_IPW_LOOP_DIS = MCA_DDRPHY_PC_CONFIG0_P0_DDR4_IPW_LOOP_DIS,
             DDR4_VLEVEL_BANK_GROUP = MCA_DDRPHY_PC_CONFIG0_P0_DDR4_VLEVEL_BANK_GROUP,
             VPROTH_PSEL_MODE = MCA_DDRPHY_PC_CONFIG0_P0_VPROTH_PSEL_MODE,
+            PBA_ENABLE = P9N2_MCA_DDRPHY_PC_CONFIG0_P0_PBA_ENABLE,
         };
 
 };
@@ -333,6 +335,21 @@ inline void set_refresh_control( fapi2::buffer<uint64_t>& o_data, const uint64_t
 }
 
 ///
+/// @brief Set PBA_ENABLE
+/// @tparam T fapi2 Target Type - defaults to fapi2::TARGET_TYPE_MCA
+/// @tparam TT traits type defaults to dp16Traits<T>
+/// @param[in,out] io_data the value of the register
+/// @param[in] i_state mss::LOW or mss::HIGH representing the state of the bit
+/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok
+///
+template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCA, typename TT = pcTraits<T> >
+inline void set_pba_enable( fapi2::buffer<uint64_t>& io_data, const mss::states i_state )
+{
+    FAPI_INF("set_pba_enable: %s", (i_state == mss::HIGH) ? "high" : "low");
+    io_data.writeBit<TT::PBA_ENABLE>(i_state);
+}
+
+///
 /// @brief set INIT_CAL_REFRESH_ALL_RANKS
 /// @tparam T fapi2 Target Type - defaults to fapi2::TARGET_TYPE_MCA
 /// @tparam TT traits type defaults to dp16Traits<T>
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/shared/mss_const.H b/src/import/chips/p9/procedures/hwp/memory/lib/shared/mss_const.H
index bbd083730..56dd35339 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/shared/mss_const.H
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/shared/mss_const.H
@@ -67,6 +67,7 @@ enum sizes
     MAX_DQ_NIBBLES = MAX_DQ_BITS / BITS_PER_NIBBLE, ///< For ISDIMMs are 18 DQ nibbles for DQ 72 bits
     MAX_DRAMS_X8 = MAX_DQ_BITS / BITS_PER_BYTE, ///< For x8's there are 9 DRAM for 72 bits
     MAX_DRAMS_X4 = MAX_DQ_BITS / BITS_PER_NIBBLE, ///< For x4's there are 18 DRAM for 72 bits
+    MAX_LRDIMM_BUFFERS = MAX_DRAMS_X8,
 
     NUM_MRW_FREQS = 4,             ///< Used for ATTR_MSS_MRW_SUPPORTED_FREQ
 
@@ -200,6 +201,10 @@ enum ffdc_function_codes
     // CW engine information
     CW_DATA_ENGINE = 117,
     CW_INFO_ENGINE = 118,
+
+    // PBA function codes
+    PBA_EXECUTE_CONTAINER = 80,
+    PBA_EXECUTE_VECTOR = 81,
 };
 
 enum states
diff --git a/src/import/chips/p9/procedures/xml/error_info/p9_memory_mss_lrdimm.xml b/src/import/chips/p9/procedures/xml/error_info/p9_memory_mss_lrdimm.xml
index 44b474c40..bab47b9ef 100644
--- a/src/import/chips/p9/procedures/xml/error_info/p9_memory_mss_lrdimm.xml
+++ b/src/import/chips/p9/procedures/xml/error_info/p9_memory_mss_lrdimm.xml
@@ -28,7 +28,7 @@
 <!-- @brief Error xml for mss_freq -->
 <!-- -->
 <!-- *HWP HWP Owner: Andre Marin <aamarin@us.ibm.com> -->
-<!-- *HWP HWP Backup: Jacob Harvey <jlharvey@us.ibm.com> -->
+<!-- *HWP HWP Backup: Stephen Glancy <sglancy@us.ibm.com> -->
 <!-- *HWP Team: Memory -->
 <!-- *HWP Level: 3 -->
 <!-- *HWP Consumed by: HB:FSP -->
@@ -77,4 +77,18 @@
     </callout>
   </hwpError>
 
+  <hwpError>
+    <rc>RC_MSS_PBA_INVALID_BUFFER</rc>
+    <description>
+      Set if a buffer is invalid after it was passed into PBA
+    </description>
+    <ffdc>BUFFER</ffdc>
+    <ffdc>MAX</ffdc>
+    <ffdc>TARGET</ffdc>
+    <callout>
+      <procedure>CODE</procedure>
+      <priority>HIGH</priority>
+    </callout>
+  </hwpError>
+
 </hwpErrors>