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author | Tsung Yeung <tyeung@us.ibm.com> | 2018-01-04 14:30:03 -0500 |
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committer | Christian R. Geddes <crgeddes@us.ibm.com> | 2018-01-17 14:18:15 -0500 |
commit | 4e84db479b0ca31d6f54cf8276e339cf566ae51e (patch) | |
tree | 60d5fa494d9794811d2e836cc5b16d8f3e99b347 /src/import/chips/p9 | |
parent | 26bbcd97d817453a114a43b661bceff5aa0131f2 (diff) | |
download | talos-hostboot-4e84db479b0ca31d6f54cf8276e339cf566ae51e.tar.gz talos-hostboot-4e84db479b0ca31d6f54cf8276e339cf566ae51e.zip |
Adds self-refresh entry/exit commands
Change-Id: Iee9654d6dced0d328148f2aaf05ccaf129ef573f
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/51486
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: STEPHEN GLANCY <sglancy@us.ibm.com>
Reviewed-by: Louis Stermole <stermole@us.ibm.com>
Reviewed-by: ANDRE A. MARIN <aamarin@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/51491
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>
Diffstat (limited to 'src/import/chips/p9')
-rw-r--r-- | src/import/chips/p9/procedures/hwp/memory/lib/ccs/ccs.H | 79 |
1 files changed, 79 insertions, 0 deletions
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/ccs/ccs.H b/src/import/chips/p9/procedures/hwp/memory/lib/ccs/ccs.H index 49da3db73..a92097f8f 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/ccs/ccs.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/ccs/ccs.H @@ -173,6 +173,15 @@ namespace mss static constexpr uint64_t CKE_HIGH = 0b1111; static constexpr uint64_t CKE_LOW = 0b0000; +// CKE setup for rank 0-7. Currently only support 0, 1, 4, 5 +// Not supported ranks will always get 0 +static constexpr uint64_t CKE_ARY[] = +{ + // 0, 1, 2, 3, + 0b0111, 0b1011, 0, 0, + // 4, 5, 6, 7 + 0b0111, 0b1011, 0, 0 +}; namespace ccs { @@ -724,6 +733,76 @@ inline instruction_t<T> precharge_all_command( const fapi2::Target<fapi2::TARGET return instruction_t<T>(i_target, i_rank, l_boilerplate_arr0, l_boilerplate_arr1); } +/// +/// @brief Setup self-refresh entry command instruction +/// @tparam T the target type of the chiplet which executes the CCS instruction +/// @tparam TT the CCS traits of the chiplet which executes the CCS instruction +/// @param[in] i_target the DIMM this instruction is headed for +/// @param[in] i_rank the rank on this dimm +/// @return the self-refresh entry command CCS instruction +/// @note THIS IS FOR DDR4 NON-LRDIMM ONLY RIGHT NOW +/// +template< fapi2::TargetType T, typename TT = ccsTraits<T> > +inline instruction_t<T> self_refresh_entry_command( const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, + const uint64_t i_rank ) +{ + fapi2::buffer<uint64_t> l_boilerplate_arr0; + fapi2::buffer<uint64_t> l_boilerplate_arr1; + + // Set all CKE to high except the rank passed in + l_boilerplate_arr0.insertFromRight<TT::ARR0_DDR_CKE, TT::ARR0_DDR_CKE_LEN>(CKE_ARY[i_rank]); + + // ACT is high + l_boilerplate_arr0.setBit<TT::ARR0_DDR_ACTN>(); + + // RAS low, CAS low, WE high + l_boilerplate_arr0.clearBit<TT::ARR0_DDR_ADDRESS_16>() + .template clearBit<TT::ARR0_DDR_ADDRESS_15>() + .template setBit<TT::ARR0_DDR_ADDRESS_14>(); + + // From DDR4 Spec table 17: + // All other bits from the command truth table are 'V', for valid (1 or 0) + + return instruction_t<T>(i_target, i_rank, l_boilerplate_arr0, l_boilerplate_arr1); +} + +/// +/// @brief Setup self-refresh exit using NOP command instruction +/// @tparam T the target type of the chiplet which executes the CCS instruction +/// @tparam TT the CCS traits of the chiplet which executes the CCS instruction +/// @param[in] i_target the DIMM this instruction is headed for +/// @param[in] i_rank the rank on this dimm +/// @return the self-refresh exit command CCS instruction +/// @note Using NOP in case SDRAM is in gear down mode and max power saving mode exit +/// @note THIS IS FOR DDR4 NON-LRDIMM ONLY RIGHT NOW +/// +template< fapi2::TargetType T, typename TT = ccsTraits<T> > +inline instruction_t<T> self_refresh_exit_command( const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, + const uint64_t i_rank ) +{ + fapi2::buffer<uint64_t> l_boilerplate_arr0; + fapi2::buffer<uint64_t> l_boilerplate_arr1; + + // Bring all CKE to high + // This in theory will take all ranks out of self refresh + // The rank passed in will see NOP (CKE = high, CS = low) + // All the other ranks will see DES (CKE = high, CS = high) + l_boilerplate_arr0.insertFromRight<TT::ARR0_DDR_CKE, TT::ARR0_DDR_CKE_LEN>(CKE_HIGH); + + // ACT is high + l_boilerplate_arr0.setBit<TT::ARR0_DDR_ACTN>(); + + // RAS high, CAS high, WE high + l_boilerplate_arr0.setBit<TT::ARR0_DDR_ADDRESS_16>() + .template setBit<TT::ARR0_DDR_ADDRESS_15>() + .template setBit<TT::ARR0_DDR_ADDRESS_14>(); + + // From DDR4 Spec table 17: + // All other bits from the command truth table are 'V', for valid (1 or 0) + + return instruction_t<T>(i_target, i_rank, l_boilerplate_arr0, l_boilerplate_arr1); +} + // // These functions are a little sugar to keep callers from doing the traits-dance to get the // appropriate bit field |