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author | Jacob Harvey <jlharvey@us.ibm.com> | 2017-07-10 16:42:09 -0500 |
---|---|---|
committer | Daniel M. Crowell <dcrowell@us.ibm.com> | 2017-08-18 10:52:26 -0400 |
commit | 25a46875b4bd8e7da5d5b2e342467ee2183e228b (patch) | |
tree | 0a5f26174ebbcb86dbe1fb407b79404dfa9a7708 /src/import/chips/p9 | |
parent | d4c08be2b76339d60f098968bfe05f5a34a19c0b (diff) | |
download | talos-hostboot-25a46875b4bd8e7da5d5b2e342467ee2183e228b.tar.gz talos-hostboot-25a46875b4bd8e7da5d5b2e342467ee2183e228b.zip |
L3 work for mss xmls
mss_spd, mss_volt, mss_general, mss_data_buffer, mss_update_errors
Change-Id: I1252d6d11900e88e0842c234c5ed815063e68ec0
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/42962
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Louis Stermole <stermole@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Reviewed-by: ANDRE A. MARIN <aamarin@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/44229
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Reviewed-by: JACOB L. HARVEY <jlharvey@us.ibm.com>
Diffstat (limited to 'src/import/chips/p9')
31 files changed, 364 insertions, 468 deletions
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs_load_ddr4.C b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs_load_ddr4.C index a9196951b..43694ac2d 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs_load_ddr4.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs_load_ddr4.C @@ -30,7 +30,7 @@ // *HWP HWP Owner: Jacob Harvey <jlharvey@us.ibm.com> // *HWP HWP Backup: Andre Marin <aamarin@us.ibm.com> // *HWP Team: Memory -// *HWP Level: 1 +// *HWP Level: 3 // *HWP Consumed by: FSP:HB #include <fapi2.H> @@ -211,7 +211,7 @@ fapi2::ReturnCode rtt_wr_to_rtt_nom_helper(const fapi2::Target<TARGET_TYPE_DIMM> FAPI_ASSERT( false, fapi2::MSS_INVALID_RTT_WR_ENCODING(). set_RTT_WR(i_rtt_wr). - set_TARGET(i_target), + set_DIMM_TARGET(i_target), "Received invalid RTT_WR value: 0x%02x for %s.", i_rtt_wr, mss::c_str(i_target) ); break; diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/eff_dimm.C b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/eff_dimm.C index 7926425a6..9df9a63a9 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/eff_dimm.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/eff_dimm.C @@ -2013,7 +2013,7 @@ fapi2::ReturnCode eff_dimm::dimm_rcbx() break; default: - FAPI_ERR("%s Error with C++ enum in eff_dimm.C. %d recieved", mss::c_str(iv_dimm), l_qs_enabled); + FAPI_ERR("%s Error with C++ enum in eff_dimm.C. %d received", mss::c_str(iv_dimm), l_qs_enabled); fapi2::Assert(false); } diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/eff_dimm.H b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/eff_dimm.H index 7daa12437..2bbcdc44d 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/eff_dimm.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/eff_dimm.H @@ -25,7 +25,7 @@ // *HWP HWP Owner: Jacob Harvey <jlharvey@us.ibm.com> // *HWP HWP Backup: Aandre Marin <aamarin@us.ibm.com> // *HWP Team: Memory -// *HWP Level: 2 +// *HWP Level: 3 // *HWP Consumed by: FSP:HB @@ -100,15 +100,16 @@ class eff_dimm iv_port_index = mss::index(iv_mca); iv_dimm_index = mss::index(iv_dimm); - FAPI_TRY( iv_pDecoder->medium_timebase(iv_mtb) ); - FAPI_TRY( iv_pDecoder->fine_timebase(iv_ftb) ); + FAPI_TRY( iv_pDecoder->medium_timebase(iv_mtb), "Failed medium timebase in eff_dimm()" ); + FAPI_TRY( iv_pDecoder->fine_timebase(iv_ftb), "Failed medium timebase in eff_dimm()" ); FAPI_TRY( clock_period(iv_dimm, iv_tCK_in_ps), "Failed to calculate clock period (tCK)" ); FAPI_TRY( mss::mrw_refresh_rate_request(iv_refresh_rate_request), "Failed mrw_temp_refresh_rate_request()" ); FAPI_TRY( mss::mrw_fine_refresh_mode(iv_refresh_mode), "Failed mrw_fine_refresh_mode()" ); - FAPI_TRY( mss::freq(find_target<fapi2::TARGET_TYPE_MCBIST>(iv_dimm), iv_freq)); + FAPI_TRY( mss::freq(find_target<fapi2::TARGET_TYPE_MCBIST>(iv_dimm), iv_freq), + "Failed accessing mss::freq in eff_dimm"); FAPI_INF("Calculated clock period - tCK (ps): %d for %s", iv_tCK_in_ps, mss::c_str(iv_dimm)); FAPI_INF("Calculated frequency (ps): %d for %s", iv_freq, mss::c_str(iv_dimm)); diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/eff_config/plug_rules.C b/src/import/chips/p9/procedures/hwp/memory/lib/eff_config/plug_rules.C index 3c458c5f7..26b391976 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/eff_config/plug_rules.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/eff_config/plug_rules.C @@ -223,7 +223,6 @@ fapi2::ReturnCode check_dead_load( const fapi2::Target<fapi2::TARGET_TYPE_MCA>& l_live_dimm = ( l_found == l_functional_dimms.end() ) ? l_live_dimm : l_plugged_dimms[0]; FAPI_ASSERT( false, fapi2::MSS_DEAD_LOAD_ON_PORT() - .set_DEAD_DIMM(l_dead_dimm) .set_FUNCTIONAL_DIMM(l_live_dimm), "%s has two DIMMs installed, but one is deconfigured (%d), so deconfiguring the other (%d) because of dead load", mss::c_str(i_target), mss::index(l_dead_dimm), mss::index(l_live_dimm)); diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/phy/ddr_phy.C b/src/import/chips/p9/procedures/hwp/memory/lib/phy/ddr_phy.C index 5755589ac..3d19b1764 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/phy/ddr_phy.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/phy/ddr_phy.C @@ -261,7 +261,7 @@ fapi2::ReturnCode setup_phase_rotator_control_registers( const fapi2::Target<TAR // From the DDR PHY workbook constexpr uint64_t CONTINUOUS_UPDATE = 0x8024; - FAPI_INF("continuous update: 0x%x", CONTINUOUS_UPDATE); + FAPI_INF("%s continuous update: 0x%x", mss::c_str(i_target), CONTINUOUS_UPDATE); constexpr uint64_t SIM_OVERRIDE = 0x8080; constexpr uint64_t PHASE_CNTL_EN = 0x8020; @@ -302,7 +302,7 @@ fapi2::ReturnCode setup_phase_rotator_control_registers( const fapi2::Target<TAR // All the MCA (and both registers) will be in the same state, so we can get the first and use it to create the // values for the others. - FAPI_INF("Write 0x%lx into the ADR SysClk Phase Rotator Control Regs", l_update); + FAPI_INF("%s Write 0x%lx into the ADR SysClk Phase Rotator Control Regs", mss::c_str(i_target), l_update); // WRCLK Phase rotators are taken care of in the phy initfile. BRS 6/16. @@ -1482,7 +1482,7 @@ fapi2::ReturnCode setup_wr_level_terminations( const fapi2::Target<fapi2::TARGET FAPI_TRY( mss::rank::get_ranks_in_pair(i_target, i_rp, l_ranks) ); FAPI_ASSERT( !l_ranks.empty(), fapi2::MSS_NO_RANKS_IN_RANK_PAIR() - .set_TARGET(i_target) + .set_MCA_TARGET(i_target) .set_RANK_PAIR(i_rp), "No ranks configured in MCA %s, rank pair %d", mss::c_str(i_target), @@ -1541,7 +1541,7 @@ fapi2::ReturnCode restore_mainline_terminations( const fapi2::Target<fapi2::TARG FAPI_TRY( mss::rank::get_ranks_in_pair(i_target, i_rp, l_ranks) ); FAPI_ASSERT( !l_ranks.empty(), fapi2::MSS_NO_RANKS_IN_RANK_PAIR() - .set_TARGET(i_target) + .set_MCA_TARGET(i_target) .set_RANK_PAIR(i_rp), "No ranks configured in MCA %s, rank pair %d", mss::c_str(i_target), i_rp ); diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/phy/dp16.C b/src/import/chips/p9/procedures/hwp/memory/lib/phy/dp16.C index c20cac543..d9a7fb8e4 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/phy/dp16.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/phy/dp16.C @@ -2774,7 +2774,7 @@ fapi2::ReturnCode process_rdvref_cal_errors( const fapi2::Target<fapi2::TARGET_T // the errors and the disables there. FAPI_ASSERT_NOEXIT(v == 0, fapi2::MSS_FAILED_RDVREF_CAL() - .set_DIMM_TARGET(i_target) + .set_MCA_TARGET(i_target) .set_REGISTER(TT::RD_VREF_CAL_ERROR_REG[l_index]) .set_VALUE(v), "DP16 failed read vref calibration on %s. register 0x%016lx value 0x%016lx", @@ -2836,7 +2836,7 @@ fapi2::ReturnCode process_wrvref_cal_errors( const fapi2::Target<fapi2::TARGET_T // Now does bitwise anding to determine what's an actual error w/ the masking FAPI_ASSERT_NOEXIT(0 == (l_mask_compare & l_data_it->first), fapi2::MSS_FAILED_WRVREF_CAL() - .set_DIMM_TARGET(i_target) + .set_MCA_TARGET(i_target) .set_REGISTER(TT::WR_VREF_ERROR_REG[l_index].first) .set_VALUE(l_data_it->first) .set_MASK(l_mask_it->first), @@ -2849,7 +2849,7 @@ fapi2::ReturnCode process_wrvref_cal_errors( const fapi2::Target<fapi2::TARGET_T FAPI_ASSERT_NOEXIT(0 == (l_mask_compare & l_data_it->second), fapi2::MSS_FAILED_WRVREF_CAL() - .set_DIMM_TARGET(i_target) + .set_MCA_TARGET(i_target) .set_REGISTER(TT::WR_VREF_ERROR_REG[l_index].second) .set_VALUE(l_data_it->second) .set_MASK(l_mask_it->second), diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/phy/phy_cntrl.C b/src/import/chips/p9/procedures/hwp/memory/lib/phy/phy_cntrl.C index d97e6cc4b..8674997fd 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/phy/phy_cntrl.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/phy/phy_cntrl.C @@ -154,18 +154,17 @@ fapi2::ReturnCode reset_config1(const fapi2::Target<TARGET_TYPE_MCA>& i_target) l_type_index = l_dimm_type[0] | l_dimm_type[1]; l_gen_index = l_dram_gen[0] | l_dram_gen[1]; - // These two checks should never be called, but better safe than seg fault - FAPI_ASSERT( l_type_index < NUM_DIMM_TYPES, - fapi2::MSS_INVALID_DIMM_TYPE() - .set_DIMM_TYPE(l_type_index) - .set_TARGET(i_target), - "Invalid DIMM configuration or DIMM type on %s", - mss::c_str(i_target)); - FAPI_ASSERT( l_gen_index < NUM_DIMM_GEN, - fapi2::MSS_PLUG_RULES_INVALID_DRAM_GEN() - .set_DRAM_GEN(l_gen_index) - .set_DIMM_TARGET(i_target), - "Invalid DIMM configuration or DRAM gen on %s", + // This check should never be called, but better safe than seg fault + FAPI_ASSERT( (l_type_index < NUM_DIMM_TYPES) && (l_gen_index < NUM_DIMM_GEN), + fapi2::MSS_PLUG_RULES_ERROR_IN_PHY() + .set_DIMM_TYPE_DIMM_0(l_dimm_type[0]) + .set_DIMM_TYPE_DIMM_1(l_dimm_type[1]) + .set_DRAM_GEN_DIMM_0(l_dram_gen[0]) + .set_DRAM_GEN_DIMM_1(l_dram_gen[1]) + .set_MCA_TARGET(i_target), + "Invalid DIMM configuration or DIMM type (%d) or DRAM_GEN (%d) on %s", + l_type_index, + l_gen_index, mss::c_str(i_target)); // FOR NIMBUS PHY (as the protocol choice above is) BRS diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/power_thermal/decoder.C b/src/import/chips/p9/procedures/hwp/memory/lib/power_thermal/decoder.C index 5a08c49f0..c25cfb35a 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/power_thermal/decoder.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/power_thermal/decoder.C @@ -27,9 +27,9 @@ /// @brief Decode MSS_MRW_PWR_CURVE_SLOPE, PWR_CURVE_INTERCEPT, and THERMAL_POWER_LIMIT /// // *HWP HWP Owner: Jacob Harvey <jlharvey@us.ibm.com> -// *HWP HWP Backup: Brian Silver <bsilver@us.ibm.com> +// *HWP HWP Backup: Andre Marin <aamarin@us.ibm.com> // *HWP Team: Memory -// *HWP Level: 2 +// *HWP Level: 3 // *HWP Consumed by: FSP:HB // fapi2 @@ -290,44 +290,45 @@ fapi2::ReturnCode get_power_attrs (const fapi2::Target<fapi2::TARGET_TYPE_MCS>& mss::dimm::kind l_kind (l_dimm); mss::power_thermal::decoder l_decoder(l_kind); - FAPI_TRY( l_decoder.generate_encoding() ); + FAPI_TRY( l_decoder.generate_encoding(), "%s Error in get_power_attrs", mss::c_str(i_mcs) ); // The first entry into these arrays must be valid // If we don't find any values, the attributes aren't found so go with some defaults if (i_slope.empty() || i_slope[0] == 0) { - FAPI_INF("ATTR_MSS_MRW_PWR_SLOPE not found!!"); + FAPI_INF("%s ATTR_MSS_MRW_PWR_SLOPE not found!!", mss::c_str(i_mcs)); o_vddr_slope [l_mca_pos][l_dimm_pos] = default_power::VDDR_SLOPE; o_total_slope [l_mca_pos][l_dimm_pos] = default_power::TOTAL_SLOPE; } else { - FAPI_TRY( l_decoder.find_slope(i_slope) ); + FAPI_TRY( l_decoder.find_slope(i_slope), "%s Error in get_power_attrs", mss::c_str(i_mcs) ); o_vddr_slope [l_mca_pos][l_dimm_pos] = l_decoder.iv_vddr_slope; o_total_slope [l_mca_pos][l_dimm_pos] = l_decoder.iv_total_slope; } if (i_intercept.empty() || i_intercept[0] == 0) { - FAPI_INF("ATTR_MSS_MRW_PWR_INTERCEPT not found!!"); + FAPI_INF("%s ATTR_MSS_MRW_PWR_INTERCEPT not found!!", mss::c_str(i_mcs)); o_total_int [l_mca_pos][l_dimm_pos] = default_power::TOTAL_INT; o_vddr_int [l_mca_pos][l_dimm_pos] = default_power::VDDR_INT; } else { - FAPI_TRY( l_decoder.find_intercept(i_intercept) ); + FAPI_TRY( l_decoder.find_intercept(i_intercept), "%s Error in get_power_attrs", mss::c_str(i_mcs) ); o_vddr_int [l_mca_pos][l_dimm_pos] = l_decoder.iv_vddr_intercept; o_total_int [l_mca_pos][l_dimm_pos] = l_decoder.iv_total_intercept; } if (i_thermal_power_limit.empty() || i_thermal_power_limit[0] == 0) { - FAPI_INF("ATTR_MSS_MRW_THERMAL_MEMORY_POWER_LIMIT not found!!"); + FAPI_INF("%s ATTR_MSS_MRW_THERMAL_MEMORY_POWER_LIMIT not found!!", mss::c_str(i_mcs)); o_thermal_power [l_mca_pos][l_dimm_pos] = default_power::THERMAL_LIMIT; } else { - FAPI_TRY( l_decoder.find_thermal_power_limit(i_thermal_power_limit) ); + FAPI_TRY( l_decoder.find_thermal_power_limit(i_thermal_power_limit), + "%s Error in get_power_attrs", mss::c_str(i_mcs) ); o_thermal_power [l_mca_pos][l_dimm_pos] = l_decoder.iv_thermal_power_limit; } } diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/power_thermal/throttle.C b/src/import/chips/p9/procedures/hwp/memory/lib/power_thermal/throttle.C index 3e7c51500..ee15073e5 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/power_thermal/throttle.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/power_thermal/throttle.C @@ -67,16 +67,19 @@ throttle::throttle( const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_mca, fapi2::R //holder for watt_target to add up for port uint32_t l_dimm_power_limits [MAX_DIMM_PER_PORT] = {}; - FAPI_TRY( mrw_max_dram_databus_util(iv_databus_port_max) ); - FAPI_TRY( mrw_dimm_power_curve_percent_uplift(iv_power_uplift) ); - FAPI_TRY( mrw_dimm_power_curve_percent_uplift_idle(iv_power_uplift_idle) ); - FAPI_TRY( dimm_thermal_limit( iv_target, iv_dimm_thermal_limit) ); - FAPI_TRY( total_pwr_intercept( iv_target, iv_pwr_int)); - FAPI_TRY( total_pwr_slope( iv_target, iv_pwr_slope)); - FAPI_TRY( runtime_mem_throttled_n_commands_per_slot(iv_target, iv_runtime_n_slot ) ); - FAPI_TRY( runtime_mem_throttled_n_commands_per_port(iv_target, iv_runtime_n_port ) ); - FAPI_TRY( mem_watt_target( iv_target, l_dimm_power_limits) ); - FAPI_TRY( mrw_mem_m_dram_clocks(iv_m_clocks) ); + FAPI_TRY( mrw_max_dram_databus_util(iv_databus_port_max), "%s Error in throttle ctor", mss::c_str(i_mca) ); + FAPI_TRY( mrw_dimm_power_curve_percent_uplift(iv_power_uplift), "%s Error in throttle ctor", mss::c_str(i_mca) ); + FAPI_TRY( mrw_dimm_power_curve_percent_uplift_idle(iv_power_uplift_idle), "%s Error in throttle ctor", + mss::c_str(i_mca) ); + FAPI_TRY( dimm_thermal_limit( iv_target, iv_dimm_thermal_limit), "%s Error in throttle ctor", mss::c_str(i_mca) ); + FAPI_TRY( total_pwr_intercept( iv_target, iv_pwr_int), "%s Error in throttle ctor", mss::c_str(i_mca) ); + FAPI_TRY( total_pwr_slope( iv_target, iv_pwr_slope), "%s Error in throttle ctor", mss::c_str(i_mca) ); + FAPI_TRY( runtime_mem_throttled_n_commands_per_slot(iv_target, iv_runtime_n_slot ), "%s Error in throttle ctor", + mss::c_str(i_mca) ); + FAPI_TRY( runtime_mem_throttled_n_commands_per_port(iv_target, iv_runtime_n_port ), "%s Error in throttle ctor", + mss::c_str(i_mca) ); + FAPI_TRY( mem_watt_target( iv_target, l_dimm_power_limits), "%s Error in throttle ctor", mss::c_str(i_mca) ); + FAPI_TRY( mrw_mem_m_dram_clocks(iv_m_clocks), "%s Error in throttle ctor", mss::c_str(i_mca) ); //Port power limit = sum of dimm power limits for ( const auto& l_dimm : mss::find_targets<TARGET_TYPE_DIMM>(iv_target) ) diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/power_thermal/throttle.H b/src/import/chips/p9/procedures/hwp/memory/lib/power_thermal/throttle.H index acb3df555..70156eb04 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/power_thermal/throttle.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/power_thermal/throttle.H @@ -28,7 +28,7 @@ /// // *HWP HWP Owner: Jacob Harvey <jlharvey@us.ibm.com> -// *HWP HWP Backup: Brian Silver <bsilver@us.ibm.com> +// *HWP HWP Backup: Andre Marin <aamarin@us.ibm.com> // *HWP Team: Memory // *HWP Level: 3 // *HWP Consumed by: FSP:HB @@ -42,19 +42,30 @@ namespace mss { namespace power_thermal { +/// +/// @brief throttle constants used in the power_thermal functions +/// enum throttle_const : size_t { - // Dram data bus utilization is bus utilization / 4 + /// Dram data bus utilization is bus utilization / 4 DRAM_BUS_UTILS = 4, - //10000 to convert to and from c% + + /// 10000 to convert to and from c% UTIL_CONVERSION = 10000, + + /// Conversion to percentage PERCENT_CONVERSION = 100, - //MIN_UTIL and IDLE_UTIL are in c% + /// MIN_UTIL is in c% MIN_UTIL = 100, + + /// IDLE_UTIL is in c% IDLE_UTIL = 0, + + /// Minimum throttle allowed for the port and or slot. If we set to 0, we brick the port MIN_THROTTLE = 1, }; + /// /// @class throttle /// @brief Determine power_thermal throttles for memory diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/spd/spd_factory.C b/src/import/chips/p9/procedures/hwp/memory/lib/spd/spd_factory.C index f61ba52b0..fd032e167 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/spd/spd_factory.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/spd/spd_factory.C @@ -27,9 +27,9 @@ /// @brief SPD factory and functions /// // *HWP HWP Owner: Andre Marin <aamarin@us.ibm.com> -// *HWP HWP Backup: Brian Silver <bsilver@us.ibm.com> +// *HWP HWP Backup: Jacob Harvey <jlharvey@us.ibm.com> // *HWP Team: Memory -// *HWP Level: 2 +// *HWP Level: 3 // *HWP Consumed by: HB:FSP // std lib @@ -122,7 +122,7 @@ fapi_try_exit: /// /// @brief Decodes SPD Revision additions level /// @param[in] i_target dimm target -/// @param[in] i_spd_data SPD data +/// @param[in] i_spd_data SPD data /// @param[out] o_value additions revision num /// @return FAPI2_RC_SUCCESS if okay /// @note Decodes SPD Byte 1 (bits 7~4). @@ -637,7 +637,7 @@ fapi2::ReturnCode raw_card_factory(const fapi2::Target<TARGET_TYPE_DIMM>& i_targ .set_DIMM_TYPE(l_dimm_type) .set_RAW_CARD_REV(l_ref_raw_card_rev) .set_DIMM_TARGET(i_target), - "Invalid reference raw card recieved for RDIMM: %d for %s", + "Invalid reference raw card received for RDIMM: %d for %s", l_ref_raw_card_rev, mss::c_str(i_target) ); break; @@ -649,17 +649,16 @@ fapi2::ReturnCode raw_card_factory(const fapi2::Target<TARGET_TYPE_DIMM>& i_targ .set_DIMM_TYPE(l_dimm_type) .set_RAW_CARD_REV(l_ref_raw_card_rev) .set_DIMM_TARGET(i_target), - "Invalid reference raw card recieved for LRDIMM: %d for %s", + "Invalid reference raw card received for LRDIMM: %d for %s", l_ref_raw_card_rev, mss::c_str(i_target)); break; default: - FAPI_ASSERT( false, fapi2::MSS_INVALID_DIMM_TYPE() .set_DIMM_TYPE(l_dimm_type) - .set_TARGET(i_target), + .set_DIMM_TARGET(i_target), "Recieved invalid dimm type: %d for %s", l_dimm_type, mss::c_str(i_target) ); break; diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/utils/checker.C b/src/import/chips/p9/procedures/hwp/memory/lib/utils/checker.C index 1aa042f58..c55657845 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/utils/checker.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/utils/checker.C @@ -28,9 +28,9 @@ /// @brief Contains common functions that perform checks /// // *HWP HWP Owner: Andre Marin <aamarin@us.ibm.com> -// *HWP FW Owner: Brian Silver <bsilver@us.ibm.com> +// *HWP FW Owner: Jacob Harvey <jlharvey@us.ibm.com> // *HWP Team: Memory -// *HWP Level: 2 +// *HWP Level: 3 // *HWP Consumed by: FSP:HB #include <fapi2.H> @@ -72,5 +72,5 @@ fapi_try_exit: return fapi2::current_err; }; -} -} +} // ns check +} // ns mss diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/utils/checker.H b/src/import/chips/p9/procedures/hwp/memory/lib/utils/checker.H index a5cbd8012..0b9a46f3f 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/utils/checker.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/utils/checker.H @@ -28,9 +28,9 @@ /// @brief Contains common functions that perform checks /// // *HWP HWP Owner: Andre Marin <aamarin@us.ibm.com> -// *HWP FW Owner: Brian Silver <bsilver@us.ibm.com> +// *HWP FW Owner: Jacob Harvey <jlharvey@us.ibm.com> // *HWP Team: Memory -// *HWP Level: 2 +// *HWP Level: 3 // *HWP Consumed by: FSP:HB #ifndef _CHECKER_H_ @@ -93,78 +93,6 @@ fapi_try_exit: } /// -/// @brief Checks homogenous DDR4 dimm configuration (e.g. DDR4) -/// @param[in] i_target the controller target -/// @return fapi2::FAPI2_RC_SUCCESS iff ok -/// -inline fapi2::ReturnCode dram_type(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target) -{ - uint8_t l_dram_gen[PORTS_PER_MCS][MAX_DIMM_PER_PORT] = {0}; - - // Retrieve DDR4 dimm attributes - FAPI_TRY(eff_dram_gen(i_target, &(l_dram_gen[0][0]))); - - // Make sure all DRAMs are DDR4 or throw an error - for (const auto& l_mca : i_target.getChildren<fapi2::TARGET_TYPE_MCA>()) - { - const auto l_port_num = mss::index(l_mca); - - for (const auto& l_dimm : l_mca.getChildren<fapi2::TARGET_TYPE_DIMM>()) - { - const auto l_dimm_num = mss::index(l_dimm); - - FAPI_INF("%s DRAM device type is %llX", - mss::c_str(l_dimm), - l_dram_gen[l_port_num][l_dimm_num]); - - // Nimbus supports only DDR4 - FAPI_ASSERT(l_dram_gen[l_port_num][l_dimm_num] == fapi2::ENUM_ATTR_EFF_DRAM_GEN_DDR4, - fapi2::MSS_UNSUPPORTED_DEV_TYPE(). - set_DEV_TYPE(l_dram_gen[l_port_num][l_dimm_num]), - "%s Incorrect DRAM device generation, DRAM generation is %llx", - mss::c_str(l_dimm), - l_dram_gen[l_port_num][l_dimm_num]); - }// dimm - }// mca - -fapi_try_exit: - return fapi2::current_err; - -}// dram_type - -/// -/// @brief Checks conditional and implements traces & exits if it fails -/// @param[in] i_target the dimm target -/// @param[in] i_conditional conditional that we are testing against -/// @param[in] i_key map key -/// @param[in] i_data additional returned data -/// @param[in] i_err_str error string to print out when conditional fails -/// @return ReturnCode -/// -inline fapi2::ReturnCode fail_for_invalid_map(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, - const bool i_conditional, - const uint64_t i_key, - const uint64_t i_data = 0, - const char* i_err_str = "") -{ - // Invalid keys won't return useful or valid data so we allow optional data - FAPI_ASSERT(i_conditional, - fapi2::MSS_INVALID_KEY(). - set_KEY(i_key). - set_DATA(i_data). - set_DIMM_TARGET(i_target), - "%s. %s Could not find value from key %d. Returned data: %d.", - c_str(i_target), - i_err_str, - i_key, - i_data); - - return fapi2::FAPI2_RC_SUCCESS; -fapi_try_exit: - return fapi2::current_err; -} - -/// /// @brief Checks to make sure ATTR_MSS_MRW_TEMP_REFRESH_MODE and ATTR_MSS_MRW_FINE_REFRESH_MODE are set correctly /// @return fapi2::FAPI2_RC_SUCCESS if okay /// @note from DDR4 DRAM Spec (79-4B) 4.9.4 page 48 diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/utils/fake_spd.C b/src/import/chips/p9/procedures/hwp/memory/lib/utils/fake_spd.C index ad8baffff..41bc0b0c6 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/utils/fake_spd.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/utils/fake_spd.C @@ -27,10 +27,10 @@ /// @file fake_spd.H /// @brief A tool to return fake (fixed) DIMM SPD for testing, development /// -// *HWP HWP Owner: Brian Silver <bsilver@us.ibm.com> -// *HWP HWP Backup: Andre Marin <aamarin@us.ibm.com> +// *HWP HWP Owner: Andre Marin <aamarin@us.ibm.com> +// *HWP HWP Backup: Jacob Harvey <jlharvey@us.ibm.com> // *HWP Team: Memory -// *HWP Level: 2 +// *HWP Level: 3 // *HWP Consumed by: HB:FSP // This shouldn't be callable by HB diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/utils/fake_spd.H b/src/import/chips/p9/procedures/hwp/memory/lib/utils/fake_spd.H index 151e0f5b4..1084494b7 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/utils/fake_spd.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/utils/fake_spd.H @@ -27,10 +27,10 @@ /// @file fake_spd.H /// @brief A tool to return fake (fixed) DIMM SPD for testing, development /// -// *HWP HWP Owner: Brian Silver <bsilver@us.ibm.com> -// *HWP HWP Backup: Andre Marin <aamarin@us.ibm.com> +// *HWP HWP Owner: Andre Marin <aamarin@us.ibm.com> +// *HWP HWP Backup: Jacob Harvey <jlharvey@us.ibm.com> // *HWP Team: Memory -// *HWP Level: 2 +// *HWP Level: 3 // *HWP Consumed by: HB:FSP // This shouldn't be callable by HB @@ -43,6 +43,9 @@ #include <fapi2.H> #include <cstdint> +/// +/// @brief SPD_TYPE class for our "fake" SPD for testing purposes +/// enum class spd_type { VBU_16GB_2RX4_2400_DDR4_RDIMM, diff --git a/src/import/chips/p9/procedures/hwp/memory/p9_mss_attr_update.C b/src/import/chips/p9/procedures/hwp/memory/p9_mss_attr_update.C index 6dd274c8f..28e240df8 100644 --- a/src/import/chips/p9/procedures/hwp/memory/p9_mss_attr_update.C +++ b/src/import/chips/p9/procedures/hwp/memory/p9_mss_attr_update.C @@ -28,9 +28,9 @@ /// @brief Programatic over-rides related to effective config /// // *HWP HWP Owner: Joe McGill <jmcgill@us.ibm.com> -// *HWP HWP Backup: Brian Silver <bsilver@us.ibm.com> +// *HWP HWP Backup: Jacob Harvey <jlharvey@us.ibm.com> // *HWP Team: Memory -// *HWP Level: 2 +// *HWP Level: 3 // *HWP Consumed by: FSP:HB @@ -94,7 +94,7 @@ p9_mss_attr_update_get_lx_offsets(const fapi2::Target<TARGET_TYPE_MCA>& i_target fapi2::MvpdKeyword& o_keyword, uint8_t& o_s_offset) { - FAPI_DBG("Start"); + FAPI_DBG("%s Start p9_mss_attr_update_get_lx_offsets", mss::c_str(i_target)); switch( mss::pos(i_target) ) { @@ -168,11 +168,10 @@ p9_mss_attr_update_get_lx_offsets(const fapi2::Target<TARGET_TYPE_MCA>& i_target } fapi_try_exit: - FAPI_DBG("End"); + FAPI_DBG("End p9_mss_attr_update_get_lx_offsets"); return fapi2::current_err; } - /// /// @brief Set ATTR_MSS_MVPD_FWMS from MVPD Lx keyword /// @param[in] i_target, the port target (e.g., MCA) @@ -185,7 +184,7 @@ p9_mss_attr_update_fwms(const fapi2::Target<TARGET_TYPE_MCA>& i_target, const uint8_t* i_record_data, const uint8_t i_f_s_offset) { - FAPI_DBG("Start"); + FAPI_DBG("Start p9_mss_attr_update_fwms"); // if group is valid, update attribute value associated with this port if (i_record_data[i_f_s_offset + @@ -221,11 +220,10 @@ p9_mss_attr_update_fwms(const fapi2::Target<TARGET_TYPE_MCA>& i_target, } fapi_try_exit: - FAPI_DBG("End"); + FAPI_DBG("End p9_mss_attr_update_fwms"); return fapi2::current_err; } - /// /// @brief Set ATTR_MSS_VREF_DAC_NIBBLE from MVPD Lx keyword /// @param[in] i_target, the port target (e.g., MCA) @@ -238,7 +236,7 @@ p9_mss_attr_update_dac_nibble(const fapi2::Target<TARGET_TYPE_MCA>& i_target, const uint8_t* i_record_data, const uint8_t i_f_s_offset) { - FAPI_DBG("Start"); + FAPI_DBG("Start p9_mss_attr_update_dac_nibble"); // if group is valid, update attribute value associated with this port if (i_record_data[i_f_s_offset + @@ -264,11 +262,10 @@ p9_mss_attr_update_dac_nibble(const fapi2::Target<TARGET_TYPE_MCA>& i_target, } fapi_try_exit: - FAPI_DBG("End"); + FAPI_DBG("End p9_mss_attr_update_dac_nibble"); return fapi2::current_err; } - /// /// @brief Set ATTR_MSS_VOLT_VDDR from MVPD Lx keyword /// @param[in] i_target, the port target (e.g., MCA) @@ -281,7 +278,7 @@ p9_mss_attr_update_vddr(const fapi2::Target<TARGET_TYPE_MCA>& i_target, const uint8_t* i_record_data, const uint8_t i_f_s_offset) { - FAPI_DBG("Start"); + FAPI_DBG("Start p9_mss_attr_update_vddr"); // if group is valid, update attribute value associated with this port if (i_record_data[i_f_s_offset + @@ -310,12 +307,10 @@ p9_mss_attr_update_vddr(const fapi2::Target<TARGET_TYPE_MCA>& i_target, } fapi_try_exit: - FAPI_DBG("End"); + FAPI_DBG("End p9_mss_attr_update_vddr"); return fapi2::current_err; } - - /// /// @brief Set ATTR_MSS_VPD_MR_DPHY_RLO from MVPD Lx keyword /// @param[in] i_target, the port target (e.g., MCA) @@ -328,7 +323,7 @@ p9_mss_attr_update_dphy_rlo(const fapi2::Target<TARGET_TYPE_MCA>& i_target, const uint8_t* i_record_data, const uint8_t i_f_s_offset) { - FAPI_DBG("Start"); + FAPI_DBG("Start p9_mss_attr_update_dphy_rlo"); // if group is valid, update attribute value associated with this port if (i_record_data[i_f_s_offset + @@ -354,7 +349,7 @@ p9_mss_attr_update_dphy_rlo(const fapi2::Target<TARGET_TYPE_MCA>& i_target, } fapi_try_exit: - FAPI_DBG("End"); + FAPI_DBG("End p9_mss_attr_update_dphy_rlo"); return fapi2::current_err; } @@ -371,7 +366,7 @@ p9_mss_attr_update_tsys_adr(const fapi2::Target<TARGET_TYPE_MCA>& i_target, const uint8_t* i_record_data, const uint8_t i_f_s_offset) { - FAPI_DBG("Start"); + FAPI_DBG("Start p9_mss_attr_update_tsys_adr"); // if group is valid, update attribute value associated with this port if (i_record_data[i_f_s_offset + @@ -394,11 +389,10 @@ p9_mss_attr_update_tsys_adr(const fapi2::Target<TARGET_TYPE_MCA>& i_target, } fapi_try_exit: - FAPI_DBG("End"); + FAPI_DBG("End p9_mss_attr_update_tsys_adr"); return fapi2::current_err; } - /// /// @brief Set ATTR_MSS_VPD_MR_TSYS_DATA from MVPD Lx keyword /// @param[in] i_target, the port target (e.g., MCA) @@ -411,7 +405,7 @@ p9_mss_attr_update_tsys_data(const fapi2::Target<TARGET_TYPE_MCA>& i_target, const uint8_t* i_record_data, const uint8_t i_f_s_offset) { - FAPI_DBG("Start"); + FAPI_DBG("Start p9_mss_attr_update_tsys_data"); // if group is valid, update attribute value associated with this port if (i_record_data[i_f_s_offset + @@ -434,7 +428,7 @@ p9_mss_attr_update_tsys_data(const fapi2::Target<TARGET_TYPE_MCA>& i_target, } fapi_try_exit: - FAPI_DBG("End"); + FAPI_DBG("End p9_mss_attr_update_tsys_data"); return fapi2::current_err; } @@ -447,7 +441,7 @@ fapi_try_exit: fapi2::ReturnCode p9_mss_attr_update_lx_mvpd(const fapi2::Target<TARGET_TYPE_MCA>& i_target) { - FAPI_INF("Start"); + FAPI_INF("Start p9_mss_attr_update_lx_mvpd"); uint32_t l_keyword_size; uint8_t l_keyword_data[CRP0_Lx_RECORD_SIZE_EXP]; @@ -470,7 +464,7 @@ p9_mss_attr_update_lx_mvpd(const fapi2::Target<TARGET_TYPE_MCA>& i_target) FAPI_ASSERT(l_keyword_size == CRP0_Lx_RECORD_SIZE_EXP, fapi2::P9_MSS_ATTR_UPDATE_MVPD_READ_ERR() - .set_TARGET(l_chip_target) + .set_CHIP_TARGET(l_chip_target) .set_KEYWORD_SIZE(l_keyword_size), "Invalid CRP0 keyword:%d record size (%s)", l_keyword, mss::c_str(l_chip_target)); @@ -490,7 +484,7 @@ p9_mss_attr_update_lx_mvpd(const fapi2::Target<TARGET_TYPE_MCA>& i_target) (l_keyword_data[Lx_VERSION_OFFSET] == Lx_V1_VALUE) || (l_keyword_data[Lx_VERSION_OFFSET] == Lx_V2_VALUE)), fapi2::P9_MSS_ATTR_UPDATE_MVPD_VERSION_ERR(). - set_TARGET(l_chip_target). + set_CHIP_TARGET(l_chip_target). set_VERSION(l_keyword_data[Lx_VERSION_OFFSET]), "Invalid CRP0 keyword:%d record version: %02X (%s)", l_keyword, l_keyword_data[Lx_VERSION_OFFSET], mss::c_str(l_chip_target)); @@ -510,7 +504,7 @@ p9_mss_attr_update_lx_mvpd(const fapi2::Target<TARGET_TYPE_MCA>& i_target) "Error from p9_mss_attr_update_tsys_data"); fapi_try_exit: - FAPI_INF("End"); + FAPI_INF("End p9_mss_attr_update_lx_mvpd"); return fapi2::current_err; } @@ -524,7 +518,7 @@ fapi_try_exit: fapi2::ReturnCode p9_mss_attr_update(const fapi2::Target<TARGET_TYPE_MCS>& i_target) { - FAPI_INF("Start"); + FAPI_INF("%s Start p9_mss_attr_update", mss::c_str(i_target) ); // if there are no DIMM, exit if (mss::count_dimm(i_target) == 0) @@ -541,6 +535,6 @@ p9_mss_attr_update(const fapi2::Target<TARGET_TYPE_MCS>& i_target) } fapi_try_exit: - FAPI_INF("End"); + FAPI_INF("%s End p9_mss_attr_update", mss::c_str(i_target) ); return fapi2::current_err; } diff --git a/src/import/chips/p9/procedures/hwp/memory/p9_mss_attr_update.H b/src/import/chips/p9/procedures/hwp/memory/p9_mss_attr_update.H index cd4c698c2..77dcbbfbf 100644 --- a/src/import/chips/p9/procedures/hwp/memory/p9_mss_attr_update.H +++ b/src/import/chips/p9/procedures/hwp/memory/p9_mss_attr_update.H @@ -28,9 +28,9 @@ /// @brief Programatic over-rides related to effective config /// // *HWP HWP Owner: Andre Marin <aamarin@us.ibm.com> -// *HWP FW Owner: Brian Silver <bsilver@us.ibm.com> +// *HWP FW Owner: Jacob Harvey <jlharvey@us.ibm.com> // *HWP Team: Memory -// *HWP Level: 1 +// *HWP Level: 3 // *HWP Consumed by: FSP:HB #ifndef __P9_MSS_ATTR_UPDATE__ diff --git a/src/import/chips/p9/procedures/hwp/memory/p9_mss_eff_config.C b/src/import/chips/p9/procedures/hwp/memory/p9_mss_eff_config.C index 4d43c83f3..5a12f1e4f 100644 --- a/src/import/chips/p9/procedures/hwp/memory/p9_mss_eff_config.C +++ b/src/import/chips/p9/procedures/hwp/memory/p9_mss_eff_config.C @@ -28,9 +28,9 @@ /// @brief Command and Control for the memory subsystem - populate attributes /// // *HWP HWP Owner: Andre Marin <aamarin@us.ibm.com> -// *HWP HWP Backup: Brian Silver <bsilver@us.ibm.com> +// *HWP HWP Backup: Jacob Harvey <jlharvey@us.ibm.com> // *HWP Team: Memory -// *HWP Level: 2 +// *HWP Level: 3 // *HWP Consumed by: FSP:HB #include <p9_mss_eff_config.H> @@ -70,12 +70,12 @@ fapi2::ReturnCode p9_mss_eff_config( const fapi2::Target<fapi2::TARGET_TYPE_MCS> fapi2::ReturnCode l_rc; std::vector< std::shared_ptr<mss::spd::decoder> > l_factory_caches; // Caches - FAPI_TRY( mss::spd::populate_decoder_caches(i_target, l_factory_caches) ); + FAPI_TRY( mss::spd::populate_decoder_caches(i_target, l_factory_caches), "Error from p9_mss_eff_config"); // Need to check dead load before we get the VPD. - // MR and MT VPD depends on DIMM ranks and freaks out if it recieves 0 ranks from DIMM 0 and 1 or more ranks for DIMM 1 - FAPI_TRY( mss::plug_rule::check_dead_load (i_target) ); - FAPI_TRY( mss::plug_rule::empty_slot_zero (i_target) ); + // MR and MT VPD depends on DIMM ranks and freaks out if it receives 0 ranks from DIMM 0 and 1 or more ranks for DIMM 1 + FAPI_TRY( mss::plug_rule::check_dead_load (i_target), "Error from p9_mss_eff_config" ); + FAPI_TRY( mss::plug_rule::empty_slot_zero (i_target), "Error from p9_mss_eff_config" ); // We need to decode the VPD. We don't do this in the ctor as we need // the rank information and for that we need the SPD caches (which we get when we populate the cache.) @@ -93,135 +93,135 @@ fapi2::ReturnCode p9_mss_eff_config( const fapi2::Target<fapi2::TARGET_TYPE_MCS> { std::shared_ptr<mss::eff_dimm> l_eff_dimm; - FAPI_TRY( mss::eff_dimm::eff_dimm_factory( l_cache, l_eff_dimm)); + FAPI_TRY( mss::eff_dimm::eff_dimm_factory( l_cache, l_eff_dimm), "Error from p9_mss_eff_config"); FAPI_INF("%s Running eff_config", mss::c_str(l_cache->iv_target) ); - FAPI_TRY( l_eff_dimm->rcd_mfg_id() ); - FAPI_TRY( l_eff_dimm->register_type() ); - FAPI_TRY( l_eff_dimm->register_rev() ); - FAPI_TRY( l_eff_dimm->dram_mfg_id() ); - FAPI_TRY( l_eff_dimm->dram_width() ); - FAPI_TRY( l_eff_dimm->dram_density() ); - FAPI_TRY( l_eff_dimm->ranks_per_dimm() ); - FAPI_TRY( l_eff_dimm->prim_die_count() ); - FAPI_TRY( l_eff_dimm->primary_stack_type() ); - FAPI_TRY( l_eff_dimm->dimm_size() ); - FAPI_TRY( l_eff_dimm->hybrid_memory_type() ); - FAPI_TRY( l_eff_dimm->dram_trefi() ); - FAPI_TRY( l_eff_dimm->dram_trfc() ); - FAPI_TRY( l_eff_dimm->dram_trfc_dlr() ); - FAPI_TRY( l_eff_dimm->rcd_mirror_mode() ); - FAPI_TRY( l_eff_dimm->dram_bank_bits() ); - FAPI_TRY( l_eff_dimm->dram_row_bits() ); - FAPI_TRY( l_eff_dimm->dram_dqs_time() ); - FAPI_TRY( l_eff_dimm->dram_tccd_l() ); - FAPI_TRY( l_eff_dimm->dimm_rc00() ); - FAPI_TRY( l_eff_dimm->dimm_rc01() ); - FAPI_TRY( l_eff_dimm->dimm_rc02() ); - FAPI_TRY( l_eff_dimm->dimm_rc03() ); - FAPI_TRY( l_eff_dimm->dimm_rc04() ); - FAPI_TRY( l_eff_dimm->dimm_rc05() ); - FAPI_TRY( l_eff_dimm->dimm_rc06_07() ); - FAPI_TRY( l_eff_dimm->dimm_rc08() ); - FAPI_TRY( l_eff_dimm->dimm_rc09() ); - FAPI_TRY( l_eff_dimm->dimm_rc0a() ); - FAPI_TRY( l_eff_dimm->dimm_rc0b() ); - FAPI_TRY( l_eff_dimm->dimm_rc0c() ); - FAPI_TRY( l_eff_dimm->dimm_rc0d() ); - FAPI_TRY( l_eff_dimm->dimm_rc0e() ); - FAPI_TRY( l_eff_dimm->dimm_rc0f() ); - FAPI_TRY( l_eff_dimm->dimm_rc1x() ); - FAPI_TRY( l_eff_dimm->dimm_rc2x() ); - FAPI_TRY( l_eff_dimm->dimm_rc3x() ); - FAPI_TRY( l_eff_dimm->dimm_rc4x() ); - FAPI_TRY( l_eff_dimm->dimm_rc5x() ); - FAPI_TRY( l_eff_dimm->dimm_rc6x() ); - FAPI_TRY( l_eff_dimm->dimm_rc7x() ); - FAPI_TRY( l_eff_dimm->dimm_rc8x() ); - FAPI_TRY( l_eff_dimm->dimm_rc9x() ); - FAPI_TRY( l_eff_dimm->dimm_rcax() ); - FAPI_TRY( l_eff_dimm->dimm_rcbx() ); - FAPI_TRY( l_eff_dimm->dram_twr() ); - FAPI_TRY( l_eff_dimm->read_burst_type() ); - FAPI_TRY( l_eff_dimm->dram_tm() ); - FAPI_TRY( l_eff_dimm->dram_cwl() ); - FAPI_TRY( l_eff_dimm->dram_lpasr() ); - FAPI_TRY( l_eff_dimm->dll_enable() ); - FAPI_TRY( l_eff_dimm->dll_reset() ); - FAPI_TRY( l_eff_dimm->write_level_enable() ); - FAPI_TRY( l_eff_dimm->output_buffer() ); - FAPI_TRY( l_eff_dimm->vref_dq_train_value() ); - FAPI_TRY( l_eff_dimm->vref_dq_train_range() ); - FAPI_TRY( l_eff_dimm->vref_dq_train_enable() ); - FAPI_TRY( l_eff_dimm->ca_parity_latency() ); - FAPI_TRY( l_eff_dimm->ca_parity_error_status() ); - FAPI_TRY( l_eff_dimm->ca_parity() ); - FAPI_TRY( l_eff_dimm->crc_error_clear() ); - FAPI_TRY( l_eff_dimm->odt_input_buffer() ); - FAPI_TRY( l_eff_dimm->post_package_repair() ); - FAPI_TRY( l_eff_dimm->read_preamble_train() ); - FAPI_TRY( l_eff_dimm->read_preamble() ); - FAPI_TRY( l_eff_dimm->write_preamble() ); - FAPI_TRY( l_eff_dimm->self_refresh_abort() ); - FAPI_TRY( l_eff_dimm->cs_to_cmd_addr_latency() ); - FAPI_TRY( l_eff_dimm->internal_vref_monitor() ); - FAPI_TRY( l_eff_dimm->max_powerdown_mode() ); - FAPI_TRY( l_eff_dimm->mpr_read_format() ); - FAPI_TRY( l_eff_dimm->temp_readout() ); - FAPI_TRY( l_eff_dimm->crc_wr_latency() ); - FAPI_TRY( l_eff_dimm->per_dram_addressability() ); - FAPI_TRY( l_eff_dimm->geardown_mode() ); - FAPI_TRY( l_eff_dimm->mpr_page() ); - FAPI_TRY( l_eff_dimm->mpr_mode() ); - FAPI_TRY( l_eff_dimm->write_crc() ); - FAPI_TRY( l_eff_dimm->zqcal_interval() ); - FAPI_TRY( l_eff_dimm->memcal_interval() ); - FAPI_TRY( l_eff_dimm->dram_trp() ); - FAPI_TRY( l_eff_dimm->dram_trcd() ); - FAPI_TRY( l_eff_dimm->dram_trc() ); - FAPI_TRY( l_eff_dimm->dram_twtr_l() ); - FAPI_TRY( l_eff_dimm->dram_twtr_s() ); - FAPI_TRY( l_eff_dimm->dram_trrd_s() ); - FAPI_TRY( l_eff_dimm->dram_trrd_l() ); - FAPI_TRY( l_eff_dimm->dram_trrd_dlr() ); - FAPI_TRY( l_eff_dimm->dram_tfaw() ); - FAPI_TRY( l_eff_dimm->dram_tfaw_dlr() ); - FAPI_TRY( l_eff_dimm->dram_tras() ); - FAPI_TRY( l_eff_dimm->dram_trtp() ); - FAPI_TRY( l_eff_dimm->read_dbi() ); - FAPI_TRY( l_eff_dimm->write_dbi() ); - FAPI_TRY( l_eff_dimm->additive_latency() ); - FAPI_TRY( l_eff_dimm->data_mask() ); - FAPI_TRY( l_eff_dimm->dimm_bc00()); - FAPI_TRY( l_eff_dimm->dimm_bc01()); - FAPI_TRY( l_eff_dimm->dimm_bc02()); - FAPI_TRY( l_eff_dimm->dimm_bc03()); - FAPI_TRY( l_eff_dimm->dimm_bc04()); - FAPI_TRY( l_eff_dimm->dimm_bc05()); - FAPI_TRY( l_eff_dimm->dimm_bc07()); - FAPI_TRY( l_eff_dimm->dimm_bc08()); - FAPI_TRY( l_eff_dimm->dimm_bc09()); - FAPI_TRY( l_eff_dimm->dimm_bc0a()); - FAPI_TRY( l_eff_dimm->dimm_bc0b()); - FAPI_TRY( l_eff_dimm->dimm_bc0c()); - FAPI_TRY( l_eff_dimm->dimm_bc0d()); - FAPI_TRY( l_eff_dimm->dimm_bc0e()); - FAPI_TRY( l_eff_dimm->dimm_bc0f()); - FAPI_TRY( l_eff_dimm->dram_rtt_nom () ); - FAPI_TRY( l_eff_dimm->dram_rtt_wr () ); - FAPI_TRY( l_eff_dimm->dram_rtt_park() ); - FAPI_TRY( l_eff_dimm->phy_seq_refresh() ); + FAPI_TRY( l_eff_dimm->rcd_mfg_id(), "Error from p9_mss_eff_config"); + FAPI_TRY( l_eff_dimm->register_type(), "Error from p9_mss_eff_config"); + FAPI_TRY( l_eff_dimm->register_rev(), "Error from p9_mss_eff_config"); + FAPI_TRY( l_eff_dimm->dram_mfg_id(), "Error from p9_mss_eff_config"); + FAPI_TRY( l_eff_dimm->dram_width(), "Error from p9_mss_eff_config"); + FAPI_TRY( l_eff_dimm->dram_density(), "Error from p9_mss_eff_config"); + FAPI_TRY( l_eff_dimm->ranks_per_dimm(), "Error from p9_mss_eff_config"); + FAPI_TRY( l_eff_dimm->prim_die_count(), "Error from p9_mss_eff_config"); + FAPI_TRY( l_eff_dimm->primary_stack_type(), "Error from p9_mss_eff_config"); + FAPI_TRY( l_eff_dimm->dimm_size(), "Error from p9_mss_eff_config"); + FAPI_TRY( l_eff_dimm->hybrid_memory_type(), "Error from p9_mss_eff_config"); + FAPI_TRY( l_eff_dimm->dram_trefi(), "Error from p9_mss_eff_config"); + FAPI_TRY( l_eff_dimm->dram_trfc(), "Error from p9_mss_eff_config"); + FAPI_TRY( l_eff_dimm->dram_trfc_dlr(), "Error from p9_mss_eff_config"); + FAPI_TRY( l_eff_dimm->rcd_mirror_mode(), "Error from p9_mss_eff_config"); + FAPI_TRY( l_eff_dimm->dram_bank_bits(), "Error from p9_mss_eff_config"); + FAPI_TRY( l_eff_dimm->dram_row_bits(), "Error from p9_mss_eff_config"); + FAPI_TRY( l_eff_dimm->dram_dqs_time(), "Error from p9_mss_eff_config"); + FAPI_TRY( l_eff_dimm->dram_tccd_l(), "Error from p9_mss_eff_config"); + FAPI_TRY( l_eff_dimm->dimm_rc00(), "Error from p9_mss_eff_config"); + FAPI_TRY( l_eff_dimm->dimm_rc01(), "Error from p9_mss_eff_config"); + FAPI_TRY( l_eff_dimm->dimm_rc02(), "Error from p9_mss_eff_config"); + FAPI_TRY( l_eff_dimm->dimm_rc03(), "Error from p9_mss_eff_config"); + FAPI_TRY( l_eff_dimm->dimm_rc04(), "Error from p9_mss_eff_config"); + FAPI_TRY( l_eff_dimm->dimm_rc05(), "Error from p9_mss_eff_config"); + FAPI_TRY( l_eff_dimm->dimm_rc06_07(), "Error from p9_mss_eff_config"); + FAPI_TRY( l_eff_dimm->dimm_rc08(), "Error from p9_mss_eff_config"); + FAPI_TRY( l_eff_dimm->dimm_rc09(), "Error from p9_mss_eff_config"); + FAPI_TRY( l_eff_dimm->dimm_rc0a(), "Error from p9_mss_eff_config"); + FAPI_TRY( l_eff_dimm->dimm_rc0b(), "Error from p9_mss_eff_config"); + FAPI_TRY( l_eff_dimm->dimm_rc0c(), "Error from p9_mss_eff_config"); + FAPI_TRY( l_eff_dimm->dimm_rc0d(), "Error from p9_mss_eff_config"); + FAPI_TRY( l_eff_dimm->dimm_rc0e(), "Error from p9_mss_eff_config"); + FAPI_TRY( l_eff_dimm->dimm_rc0f(), "Error from p9_mss_eff_config"); + FAPI_TRY( l_eff_dimm->dimm_rc1x(), "Error from p9_mss_eff_config"); + FAPI_TRY( l_eff_dimm->dimm_rc2x(), "Error from p9_mss_eff_config"); + FAPI_TRY( l_eff_dimm->dimm_rc3x(), "Error from p9_mss_eff_config"); + FAPI_TRY( l_eff_dimm->dimm_rc4x(), "Error from p9_mss_eff_config"); + FAPI_TRY( l_eff_dimm->dimm_rc5x(), "Error from p9_mss_eff_config"); + FAPI_TRY( l_eff_dimm->dimm_rc6x(), "Error from p9_mss_eff_config"); + FAPI_TRY( l_eff_dimm->dimm_rc7x(), "Error from p9_mss_eff_config"); + FAPI_TRY( l_eff_dimm->dimm_rc8x(), "Error from p9_mss_eff_config"); + FAPI_TRY( l_eff_dimm->dimm_rc9x(), "Error from p9_mss_eff_config"); + FAPI_TRY( l_eff_dimm->dimm_rcax(), "Error from p9_mss_eff_config"); + FAPI_TRY( l_eff_dimm->dimm_rcbx(), "Error from p9_mss_eff_config"); + FAPI_TRY( l_eff_dimm->dram_twr(), "Error from p9_mss_eff_config"); + FAPI_TRY( l_eff_dimm->read_burst_type(), "Error from p9_mss_eff_config"); + FAPI_TRY( l_eff_dimm->dram_tm(), "Error from p9_mss_eff_config"); + FAPI_TRY( l_eff_dimm->dram_cwl(), "Error from p9_mss_eff_config"); + FAPI_TRY( l_eff_dimm->dram_lpasr(), "Error from p9_mss_eff_config"); + FAPI_TRY( l_eff_dimm->dll_enable(), "Error from p9_mss_eff_config"); + FAPI_TRY( l_eff_dimm->dll_reset(), "Error from p9_mss_eff_config"); + FAPI_TRY( l_eff_dimm->write_level_enable(), "Error from p9_mss_eff_config"); + FAPI_TRY( l_eff_dimm->output_buffer(), "Error from p9_mss_eff_config"); + FAPI_TRY( l_eff_dimm->vref_dq_train_value(), "Error from p9_mss_eff_config"); + FAPI_TRY( l_eff_dimm->vref_dq_train_range(), "Error from p9_mss_eff_config"); + FAPI_TRY( l_eff_dimm->vref_dq_train_enable(), "Error from p9_mss_eff_config"); + FAPI_TRY( l_eff_dimm->ca_parity_latency(), "Error from p9_mss_eff_config"); + FAPI_TRY( l_eff_dimm->ca_parity_error_status(), "Error from p9_mss_eff_config"); + FAPI_TRY( l_eff_dimm->ca_parity(), "Error from p9_mss_eff_config"); + FAPI_TRY( l_eff_dimm->crc_error_clear(), "Error from p9_mss_eff_config"); + FAPI_TRY( l_eff_dimm->odt_input_buffer(), "Error from p9_mss_eff_config"); + FAPI_TRY( l_eff_dimm->post_package_repair(), "Error from p9_mss_eff_config"); + FAPI_TRY( l_eff_dimm->read_preamble_train(), "Error from p9_mss_eff_config"); + FAPI_TRY( l_eff_dimm->read_preamble(), "Error from p9_mss_eff_config"); + FAPI_TRY( l_eff_dimm->write_preamble(), "Error from p9_mss_eff_config"); + FAPI_TRY( l_eff_dimm->self_refresh_abort(), "Error from p9_mss_eff_config"); + FAPI_TRY( l_eff_dimm->cs_to_cmd_addr_latency(), "Error from p9_mss_eff_config"); + FAPI_TRY( l_eff_dimm->internal_vref_monitor(), "Error from p9_mss_eff_config"); + FAPI_TRY( l_eff_dimm->max_powerdown_mode(), "Error from p9_mss_eff_config"); + FAPI_TRY( l_eff_dimm->mpr_read_format(), "Error from p9_mss_eff_config"); + FAPI_TRY( l_eff_dimm->temp_readout(), "Error from p9_mss_eff_config"); + FAPI_TRY( l_eff_dimm->crc_wr_latency(), "Error from p9_mss_eff_config"); + FAPI_TRY( l_eff_dimm->per_dram_addressability(), "Error from p9_mss_eff_config"); + FAPI_TRY( l_eff_dimm->geardown_mode(), "Error from p9_mss_eff_config"); + FAPI_TRY( l_eff_dimm->mpr_page(), "Error from p9_mss_eff_config"); + FAPI_TRY( l_eff_dimm->mpr_mode(), "Error from p9_mss_eff_config"); + FAPI_TRY( l_eff_dimm->write_crc(), "Error from p9_mss_eff_config"); + FAPI_TRY( l_eff_dimm->zqcal_interval(), "Error from p9_mss_eff_config"); + FAPI_TRY( l_eff_dimm->memcal_interval(), "Error from p9_mss_eff_config"); + FAPI_TRY( l_eff_dimm->dram_trp(), "Error from p9_mss_eff_config"); + FAPI_TRY( l_eff_dimm->dram_trcd(), "Error from p9_mss_eff_config"); + FAPI_TRY( l_eff_dimm->dram_trc(), "Error from p9_mss_eff_config"); + FAPI_TRY( l_eff_dimm->dram_twtr_l(), "Error from p9_mss_eff_config"); + FAPI_TRY( l_eff_dimm->dram_twtr_s(), "Error from p9_mss_eff_config"); + FAPI_TRY( l_eff_dimm->dram_trrd_s(), "Error from p9_mss_eff_config"); + FAPI_TRY( l_eff_dimm->dram_trrd_l(), "Error from p9_mss_eff_config"); + FAPI_TRY( l_eff_dimm->dram_trrd_dlr(), "Error from p9_mss_eff_config"); + FAPI_TRY( l_eff_dimm->dram_tfaw(), "Error from p9_mss_eff_config"); + FAPI_TRY( l_eff_dimm->dram_tfaw_dlr(), "Error from p9_mss_eff_config"); + FAPI_TRY( l_eff_dimm->dram_tras(), "Error from p9_mss_eff_config"); + FAPI_TRY( l_eff_dimm->dram_trtp(), "Error from p9_mss_eff_config"); + FAPI_TRY( l_eff_dimm->read_dbi(), "Error from p9_mss_eff_config"); + FAPI_TRY( l_eff_dimm->write_dbi(), "Error from p9_mss_eff_config"); + FAPI_TRY( l_eff_dimm->additive_latency(), "Error from p9_mss_eff_config"); + FAPI_TRY( l_eff_dimm->data_mask(), "Error from p9_mss_eff_config"); + FAPI_TRY( l_eff_dimm->dimm_bc00(), "Error from p9_mss_eff_config"); + FAPI_TRY( l_eff_dimm->dimm_bc01(), "Error from p9_mss_eff_config"); + FAPI_TRY( l_eff_dimm->dimm_bc02(), "Error from p9_mss_eff_config"); + FAPI_TRY( l_eff_dimm->dimm_bc03(), "Error from p9_mss_eff_config"); + FAPI_TRY( l_eff_dimm->dimm_bc04(), "Error from p9_mss_eff_config"); + FAPI_TRY( l_eff_dimm->dimm_bc05(), "Error from p9_mss_eff_config"); + FAPI_TRY( l_eff_dimm->dimm_bc07(), "Error from p9_mss_eff_config"); + FAPI_TRY( l_eff_dimm->dimm_bc08(), "Error from p9_mss_eff_config"); + FAPI_TRY( l_eff_dimm->dimm_bc09(), "Error from p9_mss_eff_config"); + FAPI_TRY( l_eff_dimm->dimm_bc0a(), "Error from p9_mss_eff_config"); + FAPI_TRY( l_eff_dimm->dimm_bc0b(), "Error from p9_mss_eff_config"); + FAPI_TRY( l_eff_dimm->dimm_bc0c(), "Error from p9_mss_eff_config"); + FAPI_TRY( l_eff_dimm->dimm_bc0d(), "Error from p9_mss_eff_config"); + FAPI_TRY( l_eff_dimm->dimm_bc0e(), "Error from p9_mss_eff_config"); + FAPI_TRY( l_eff_dimm->dimm_bc0f(), "Error from p9_mss_eff_config"); + FAPI_TRY( l_eff_dimm->dram_rtt_nom (), "Error from p9_mss_eff_config"); + FAPI_TRY( l_eff_dimm->dram_rtt_wr (), "Error from p9_mss_eff_config"); + FAPI_TRY( l_eff_dimm->dram_rtt_park(), "Error from p9_mss_eff_config"); + FAPI_TRY( l_eff_dimm->phy_seq_refresh(), "Error from p9_mss_eff_config"); // Sets up the calibration steps - FAPI_TRY( l_eff_dimm->cal_step_enable() ); - FAPI_TRY( l_eff_dimm->rdvref_enable_bit() ); + FAPI_TRY( l_eff_dimm->cal_step_enable(), "Error from p9_mss_eff_config"); + FAPI_TRY( l_eff_dimm->rdvref_enable_bit(), "Error from p9_mss_eff_config"); //Let's do some checking - FAPI_TRY( mss::check::temp_refresh_mode()); + FAPI_TRY( mss::check::temp_refresh_mode(), "Error from p9_mss_eff_config"); }// dimm // Check plug rules. We check the MCS, and this will iterate down to children as needed. - FAPI_TRY( mss::plug_rule::enforce_plug_rules(i_target) ); + FAPI_TRY( mss::plug_rule::enforce_plug_rules(i_target), "Error from p9_mss_eff_config"); fapi_try_exit: return fapi2::current_err; diff --git a/src/import/chips/p9/procedures/hwp/memory/p9_mss_eff_config.H b/src/import/chips/p9/procedures/hwp/memory/p9_mss_eff_config.H index ea7c1a3e5..ce705f3b7 100644 --- a/src/import/chips/p9/procedures/hwp/memory/p9_mss_eff_config.H +++ b/src/import/chips/p9/procedures/hwp/memory/p9_mss_eff_config.H @@ -28,9 +28,9 @@ /// @brief Command and Control for the memory subsystem - populate attributes /// // *HWP HWP Owner: Andre Marin <aamarin@us.ibm.com> -// *HWP HWP Backup: Brian Silver <bsilver@us.ibm.com> +// *HWP HWP Backup: Jacob Harvey <jlharvey@us.ibm.com> // *HWP Team: Memory -// *HWP Level: 2 +// *HWP Level: 3 // *HWP Consumed by: FSP:HB #ifndef __P9_MSS_EFF_CONFIG__ diff --git a/src/import/chips/p9/procedures/hwp/memory/p9_mss_eff_config_thermal.C b/src/import/chips/p9/procedures/hwp/memory/p9_mss_eff_config_thermal.C index 716d80f8f..0d99ab478 100644 --- a/src/import/chips/p9/procedures/hwp/memory/p9_mss_eff_config_thermal.C +++ b/src/import/chips/p9/procedures/hwp/memory/p9_mss_eff_config_thermal.C @@ -28,9 +28,9 @@ /// @brief Perform thermal calculations as part of the effective configuration /// // *HWP HWP Owner: Jacob Harvey <jlharvey@us.ibm.com> -// *HWP HWP Backup: Brian Silver <bsilver@us.ibm.com> +// *HWP HWP Backup: Andre Marin <aamarin@us.ibm.com> // *HWP Team: Memory -// *HWP Level: 2 +// *HWP Level: 3 // *HWP Consumed by: FSP:HB #include <fapi2.H> @@ -74,10 +74,10 @@ extern "C" std::vector<fapi2::buffer< uint64_t>> l_thermal_power_limit = {}; //Get the vectors of power curves and thermal power limits to convert to buffers - FAPI_TRY( mss::mrw_pwr_slope (l_tslope.data() )); - FAPI_TRY( mss::mrw_pwr_intercept (l_tintercept.data()) ); - FAPI_TRY( mss::mrw_thermal_memory_power_limit (l_tthermal_power_limit.data()) ); - FAPI_TRY( mss::power_thermal::set_runtime_m_and_watt_limit(i_targets)); + FAPI_TRY( mss::mrw_pwr_slope (l_tslope.data()), "Error in p9_mss_eff_config_thermal"); + FAPI_TRY( mss::mrw_pwr_intercept (l_tintercept.data()), "Error in p9_mss_eff_config_thermal" ); + FAPI_TRY( mss::mrw_thermal_memory_power_limit (l_tthermal_power_limit.data()), "Error in p9_mss_eff_config_thermal" ); + FAPI_TRY( mss::power_thermal::set_runtime_m_and_watt_limit(i_targets), "Error in p9_mss_eff_config_thermal"); for (size_t i = 0; i < mss::power_thermal::SIZE_OF_POWER_CURVES_ATTRS; ++i) { @@ -133,7 +133,7 @@ extern "C" l_thermal_power)); //Sets throttles to max_databus_util value FAPI_INF("Restoring throttles"); - FAPI_TRY( mss::power_thermal::restore_runtime_throttles(l_mcs)); + FAPI_TRY( mss::power_thermal::restore_runtime_throttles(l_mcs), "Error in p9_mss_eff_config_thermal"); //Set the power attribute (TOTAL_PWR) to just VDDR for the POWER bulk_pwr_throttles, restore to vddr+vpp later for OCC FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_MSS_TOTAL_PWR_SLOPE, @@ -158,7 +158,7 @@ extern "C" //Set runtime throttles to worst case between ATTR_MSS_MEM_THROTTLED_N_COMMANDS_PER_SLOT //and ATTR_MSS_MEM_RUNTIME_THROTTLED_N_COMMANDS_PER_SLOT and the _PORT equivalents also FAPI_INF("Starting update"); - FAPI_TRY( mss::power_thermal::update_runtime_throttles (i_targets) ); + FAPI_TRY( mss::power_thermal::update_runtime_throttles (i_targets), "Error in p9_mss_eff_config_thermal" ); FAPI_INF("finished update"); //Set VDDR+VPP power curve values @@ -196,7 +196,7 @@ extern "C" FAPI_EXEC_HWP(l_rc, p9_mss_bulk_pwr_throttles, i_targets, mss::throttle_type::THERMAL); FAPI_TRY(l_rc, "Failed running p9_mss_bulk_pwr_throttles with THERMAL throttling in p9_mss_eff_config_thermal"); //Update everything to worst case - FAPI_TRY( mss::power_thermal::update_runtime_throttles (i_targets) ); + FAPI_TRY( mss::power_thermal::update_runtime_throttles (i_targets), "Error in p9_mss_eff_config_thermal" ); //Done FAPI_INF( "End effective config thermal"); diff --git a/src/import/chips/p9/procedures/hwp/memory/p9_mss_volt.C b/src/import/chips/p9/procedures/hwp/memory/p9_mss_volt.C index 77c9afd6c..04a6c0b34 100644 --- a/src/import/chips/p9/procedures/hwp/memory/p9_mss_volt.C +++ b/src/import/chips/p9/procedures/hwp/memory/p9_mss_volt.C @@ -29,7 +29,6 @@ /// // *HWP HWP Owner: Jacob Harvey <jlharvey@us.ibm.com> // *HWP HWP Backup: Andre A. Marin <aamarin@us.ibm.com> -// *HWP FW Owner: Brian Silver <bsilver@us.ibm.com> // *HWP Team: Memory // *HWP Level: 3 // *HWP Consumed by: FSP:HB @@ -90,18 +89,21 @@ extern "C" //Check to make sure 1.2 V is both operable and endurant, fail if it is not FAPI_ASSERT ( (l_dimm_nominal == mss::spd::OPERABLE) && (l_dimm_endurant == mss::spd::ENDURANT), fapi2::MSS_VOLT_DDR_TYPE_REQUIRED_VOLTAGE(). - set_OPERABLE(l_dimm_nominal). - set_ENDURANT(l_dimm_endurant). + set_ACTUAL_OPERABLE(l_dimm_nominal). + set_ACTUAL_ENDURANT(l_dimm_endurant). + set_EXPECTED_OPERABLE(mss::spd::OPERABLE). + set_EXPECTED_ENDURANT(mss::spd::ENDURANT). set_DIMM_TARGET(l_cache->iv_target), - "%s: DIMM is not operable (%d)" - " and/or endurant (%d) at 1.2V", + "%s: DIMM is not operable (%d) expected (%d)" + " and/or endurant (%d) expected (%d) at 1.2V", mss::c_str(l_cache->iv_target), l_dimm_nominal, - l_dimm_endurant); + mss::spd::OPERABLE, + l_dimm_endurant, + mss::spd::ENDURANT); } // l_dimm // Set the attributes for this MCS, values are in mss_const.H - // TK : will need to change attribute target according to voltage rails in the future FAPI_TRY (mss::set_voltage_attributes (l_mcs, mss::DDR4_NOMINAL_VOLTAGE, mss::DDR4_VPP_VOLTAGE), diff --git a/src/import/chips/p9/procedures/hwp/memory/p9_mss_volt.H b/src/import/chips/p9/procedures/hwp/memory/p9_mss_volt.H index dd3257d22..8a80d30f2 100644 --- a/src/import/chips/p9/procedures/hwp/memory/p9_mss_volt.H +++ b/src/import/chips/p9/procedures/hwp/memory/p9_mss_volt.H @@ -29,7 +29,6 @@ /// // *HWP HWP Owner: Jacob Harvey <jlharvey@us.ibm.com> // *HWP HWP Backup: Andre A. Marin <aamarin@us.ibm.com> -// *HWP FW Owner: Brian Silver <bsilver@us.ibm.com> // *HWP Team: Memory // *HWP Level: 3 // *HWP Consumed by: FSP:HB diff --git a/src/import/chips/p9/procedures/xml/error_info/p9_memory_mss_data_buffer.xml b/src/import/chips/p9/procedures/xml/error_info/p9_memory_mss_data_buffer.xml index b90adede4..1887f83d9 100644 --- a/src/import/chips/p9/procedures/xml/error_info/p9_memory_mss_data_buffer.xml +++ b/src/import/chips/p9/procedures/xml/error_info/p9_memory_mss_data_buffer.xml @@ -45,12 +45,20 @@ </description> <ffdc>NUM_PKG_RANKS</ffdc> <callout> - <target>DIMM_TARGET</target> + <procedure>MEMORY_PLUGGING_ERROR</procedure> <priority>HIGH</priority> </callout> + <callout> + <target>DIMM_TARGET</target> + <priority>MEDIUM</priority> + </callout> <deconfigure> <target>DIMM_TARGET</target> </deconfigure> + <callout> + <procedure>CODE</procedure> + <priority>LOW</priority> + </callout> </hwpError> <hwpError> @@ -65,6 +73,10 @@ <ffdc>AADR</ffdc> <ffdc>AAER</ffdc> <callout> + <procedure>CODE</procedure> + <priority>LOW</priority> + </callout> + <callout> <target>DIMM_TARGET</target> <priority>HIGH</priority> </callout> @@ -72,5 +84,4 @@ <target>DIMM_TARGET</target> </deconfigure> </hwpError> - </hwpErrors> diff --git a/src/import/chips/p9/procedures/xml/error_info/p9_memory_mss_ddr_phy_reset.xml b/src/import/chips/p9/procedures/xml/error_info/p9_memory_mss_ddr_phy_reset.xml index 3f110887a..32825259c 100644 --- a/src/import/chips/p9/procedures/xml/error_info/p9_memory_mss_ddr_phy_reset.xml +++ b/src/import/chips/p9/procedures/xml/error_info/p9_memory_mss_ddr_phy_reset.xml @@ -561,6 +561,23 @@ </hwpError> <hwpError> + <rc>RC_MSS_PLUG_RULES_ERROR_IN_PHY</rc> + <description> + Error in mss_ddr_phy_reset due error on DIMM attributes + Should have been caught in plug rules + </description> + <ffdc>DRAM_GEN_DIMM_0</ffdc> + <ffdc>DRAM_GEN_DIMM_1</ffdc> + <ffdc>DIMM_TYPE_DIMM_0</ffdc> + <ffdc>DIMM_TYPE_DIMM_1</ffdc> + <ffdc>MCA_TARGET</ffdc> + <callout> + <procedure>CODE</procedure> + <priority>HIGH</priority> + </callout> +</hwpError> + +<hwpError> <rc>RC_MSS_DDR_PHY_RESET_PORT_FIRS_REPORTED</rc> <description> One or more ports noted a set error bit during PHY reset diff --git a/src/import/chips/p9/procedures/xml/error_info/p9_memory_mss_draminit_training.xml b/src/import/chips/p9/procedures/xml/error_info/p9_memory_mss_draminit_training.xml index a9c92df3b..7bb746450 100644 --- a/src/import/chips/p9/procedures/xml/error_info/p9_memory_mss_draminit_training.xml +++ b/src/import/chips/p9/procedures/xml/error_info/p9_memory_mss_draminit_training.xml @@ -577,23 +577,23 @@ <ffdc>VALUE</ffdc> <collectRegisterFfdc> <id>REG_FFDC_MSS_DRAMINIT_TRAINING_ERROR_INFO</id> - <target>DIMM_TARGET</target> + <target>MCA_TARGET</target> <targetType>TARGET_TYPE_MCA</targetType> </collectRegisterFfdc> <collectRegisterFfdc> <id>REG_FFDC_MSS_DRAMINIT_TRAINING_FAILURE_DISABLE_REGS</id> - <target>DIMM_TARGET</target> + <target>MCA_TARGET</target> <targetType>TARGET_TYPE_MCA</targetType> </collectRegisterFfdc> <callout> - <target>DIMM_TARGET</target> + <target>MCA_TARGET</target> <priority>HIGH</priority> </callout> <deconfigure> - <target>DIMM_TARGET</target> + <target>MCA_TARGET</target> </deconfigure> <gard> - <target>DIMM_TARGET</target> + <target>MCA_TARGET</target> </gard> </hwpError> @@ -675,19 +675,19 @@ <ffdc>MASK</ffdc> <collectRegisterFfdc> <id>REG_FFDC_MSS_DRAMINIT_TRAINING_ERROR_INFO</id> - <target>DIMM_TARGET</target> + <target>MCA_TARGET</target> <targetType>TARGET_TYPE_MCA</targetType> </collectRegisterFfdc> <collectRegisterFfdc> <id>REG_FFDC_MSS_DRAMINIT_TRAINING_FAILURE_DISABLE_REGS</id> - <target>DIMM_TARGET</target> + <target>MCA_TARGET</target> <targetType>TARGET_TYPE_MCA</targetType> </collectRegisterFfdc> <deconfigure> - <target>DIMM_TARGET</target> + <target>MCA_TARGET</target> </deconfigure> <gard> - <target>DIMM_TARGET</target> + <target>MCA_TARGET</target> </gard> </hwpError> diff --git a/src/import/chips/p9/procedures/xml/error_info/p9_memory_mss_eff_config.xml b/src/import/chips/p9/procedures/xml/error_info/p9_memory_mss_eff_config.xml index ae4c7860c..049a4cc24 100644 --- a/src/import/chips/p9/procedures/xml/error_info/p9_memory_mss_eff_config.xml +++ b/src/import/chips/p9/procedures/xml/error_info/p9_memory_mss_eff_config.xml @@ -49,22 +49,6 @@ </hwpError> <hwpError> - <rc>RC_MSS_UNSUPPORTED_DEV_TYPE</rc> - <description>Device type is not DDR4 or DDR3</description> - <ffdc>DEV_TYPE</ffdc> - <callout> - <target>DIMM_TARGET</target> - <priority>HIGH</priority> - </callout> - <deconfigure> - <target>DIMM_TARGET</target> - </deconfigure> - <gard> - <target>DIMM_TARGET</target> - </gard> - </hwpError> - - <hwpError> <rc>RC_MSS_INVALID_FINE_REFRESH_MODE_WITH_TEMP_REFRESH_MODE_ENABLED</rc> <description> Invalid fine refresh mode received due to temperature refresh mode being enabled diff --git a/src/import/chips/p9/procedures/xml/error_info/p9_memory_mss_general_errors.xml b/src/import/chips/p9/procedures/xml/error_info/p9_memory_mss_general_errors.xml index 74743b025..fe302cb4d 100644 --- a/src/import/chips/p9/procedures/xml/error_info/p9_memory_mss_general_errors.xml +++ b/src/import/chips/p9/procedures/xml/error_info/p9_memory_mss_general_errors.xml @@ -28,7 +28,7 @@ <!-- @brief Error xml for timing.H --> <!-- --> <!-- *HWP HWP Owner: Andre Marin <aamarin@us.ibm.com> --> -<!-- *HWP HWP Backup: Brian Silver <bsilver@us.ibm.com> --> +<!-- *HWP HWP Backup: Jacob Harvey <jlharvey@us.ibm.com> --> <!-- *HWP Team: Memory --> <!-- *HWP Level: 3 --> <!-- *HWP Consumed by: HB:FSP --> @@ -37,22 +37,6 @@ <hwpErrors> <hwpError> - <rc>RC_MSS_LOOKUP_FAILED</rc> - <description> - Conditional that tests whether a certain key value is located in a map (hence, lookup). - </description> - <ffdc>KEY</ffdc> - <ffdc>DATA</ffdc> - <callout> - <target>TARGET</target> - <priority>HIGH</priority> - </callout> - <deconfigure> - <target>TARGET</target> - </deconfigure> - </hwpError> - - <hwpError> <rc>RC_MSS_INVALID_DIMM_TYPE</rc> <description> An invalid/unsupported DIMM type was received. This is possibly due @@ -60,44 +44,46 @@ </description> <ffdc>DIMM_TYPE</ffdc> <callout> - <target>TARGET</target> + <procedure>MEMORY_PLUGGING_ERROR</procedure> <priority>HIGH</priority> </callout> + <callout> + <target>DIMM_TARGET</target> + <priority>MEDIUM</priority> + </callout> <deconfigure> - <target>TARGET</target> + <target>DIMM_TARGET</target> </deconfigure> + <callout> + <procedure>CODE</procedure> + <priority>LOW</priority> + </callout> </hwpError> <hwpError> <rc>RC_MSS_INVALID_RTT_WR_ENCODING</rc> <description> - An invalid/unsupported RTT_WR encoding was received, possibly due to VPD error or bad - setting of ATTR_EFF_DRAM_RTT_WR attribute. + An invalid/unsupported RTT_WR encoding was received </description> <ffdc>RTT_WR</ffdc> + <ffdc>DIMM_TARGET</ffdc> <callout> - <target>TARGET</target> + <procedure>CODE</procedure> <priority>HIGH</priority> </callout> - <deconfigure> - <target>TARGET</target> - </deconfigure> </hwpError> <hwpError> <rc>RC_MSS_NO_RANKS_IN_RANK_PAIR</rc> <description> - A rank pair was received with no configured ranks when setting up terminations - for write leveling calibration. + A rank pair was received with no configured ranks </description> <ffdc>RANK_PAIR</ffdc> + <ffdc>MCA_TARGET</ffdc> <callout> - <target>TARGET</target> + <procedure>CODE</procedure> <priority>HIGH</priority> </callout> - <deconfigure> - <target>TARGET</target> - </deconfigure> </hwpError> </hwpErrors> diff --git a/src/import/chips/p9/procedures/xml/error_info/p9_memory_mss_plug_rules.xml b/src/import/chips/p9/procedures/xml/error_info/p9_memory_mss_plug_rules.xml index 89020e280..724d789fc 100644 --- a/src/import/chips/p9/procedures/xml/error_info/p9_memory_mss_plug_rules.xml +++ b/src/import/chips/p9/procedures/xml/error_info/p9_memory_mss_plug_rules.xml @@ -69,12 +69,8 @@ <priority>HIGH</priority> </callout> <callout> - <target>DEAD_DIMM</target> - <priority>LOW</priority> - </callout> - <callout> <target>FUNCTIONAL_DIMM</target> - <priority>LOW</priority> + <priority>NONE</priority> </callout> <deconfigure> <target>FUNCTIONAL_DIMM</target> diff --git a/src/import/chips/p9/procedures/xml/error_info/p9_memory_mss_spd_decode.xml b/src/import/chips/p9/procedures/xml/error_info/p9_memory_mss_spd_decode.xml index dde6983d6..7dfc0d5a6 100644 --- a/src/import/chips/p9/procedures/xml/error_info/p9_memory_mss_spd_decode.xml +++ b/src/import/chips/p9/procedures/xml/error_info/p9_memory_mss_spd_decode.xml @@ -38,10 +38,18 @@ <hwpError> <rc>RC_MSS_BAD_SPD</rc> - <description>Bad SPD data recieved.</description> + <description> + Bad SPD data received. + Settings are incorrect within SPD. + This could be code problem (decoding) or bad SPD + </description> <ffdc>VALUE</ffdc> <ffdc>BYTE</ffdc> <callout> + <procedure>CODE</procedure> + <priority>MEDIUM</priority> + </callout> + <callout> <target>DIMM_TARGET</target> <priority>HIGH</priority> </callout> @@ -53,7 +61,7 @@ <hwpError> <rc>RC_MSS_INVALID_DIMM_REV_COMBO</rc> <description> - Recieved a dimm type (e.g. RDIMM, LRDIMM) and SPD revision + Received a dimm type (e.g. RDIMM, LRDIMM) and SPD revision (e.g. 1.0, 1.1) combination unsupported by the spd_decoder object "factory" </description> @@ -61,44 +69,43 @@ <ffdc>ENCODING_REV</ffdc> <ffdc>ADDITIONS_REV</ffdc> <callout> - <target>DIMM_TARGET</target> + <procedure>MEMORY_PLUGGING_ERROR</procedure> <priority>HIGH</priority> </callout> - <deconfigure> - <target>DIMM_TARGET</target> - </deconfigure> - </hwpError> - - <hwpError> - <rc>RC_MSS_INVALID_CACHE</rc> - <description> - Bad SPD cache. Unable to find decoder factory instance from dimm position. - </description> - <ffdc>DIMM_POS</ffdc> <callout> <target>DIMM_TARGET</target> - <priority>HIGH</priority> + <priority>LOW</priority> </callout> <deconfigure> <target>DIMM_TARGET</target> </deconfigure> + <callout> + <procedure>CODE</procedure> + <priority>MEDIUM</priority> + </callout> </hwpError> <hwpError> <rc>RC_MSS_INVALID_RAW_CARD</rc> <description> - Recieved a raw card that currently isn't supported in code + Received a raw card that isn't currently supported in code </description> <ffdc>DIMM_TYPE</ffdc> <ffdc>RAW_CARD_REV</ffdc> <callout> - <target>DIMM_TARGET</target> + <procedure>MEMORY_PLUGGING_ERROR</procedure> <priority>HIGH</priority> </callout> + <callout> + <procedure>CODE</procedure> + <priority>MEDIUM</priority> + </callout> + <callout> + <target>DIMM_TARGET</target> + <priority>LOW</priority> + </callout> <deconfigure> <target>DIMM_TARGET</target> </deconfigure> </hwpError> - - </hwpErrors> diff --git a/src/import/chips/p9/procedures/xml/error_info/p9_memory_mss_volt.xml b/src/import/chips/p9/procedures/xml/error_info/p9_memory_mss_volt.xml index d7ab24885..73f3c1b0a 100644 --- a/src/import/chips/p9/procedures/xml/error_info/p9_memory_mss_volt.xml +++ b/src/import/chips/p9/procedures/xml/error_info/p9_memory_mss_volt.xml @@ -30,86 +30,28 @@ <!-- *HWP HWP Owner: Andre Marin <aamarin@us.ibm.com> --> <!-- *HWP HWP Backup: Brian Silver <bsilver@us.ibm.com> --> <!-- *HWP Team: Memory --> -<!-- *HWP Level: 2 --> +<!-- *HWP Level: 3 --> <!-- *HWP Consumed by: HB:FSP --> <!-- --> -<!-- //TK This needs to be cleaned up after mss_volt is refactored, ported from p8 - AAM --> <hwpErrors> - -<!-- Original Source for RC_MSS_VOLT_UNRECOGNIZED_DRAM_DEVICE_TYPE memory_errors.xml --> - <hwpError> - <rc>RC_MSS_VOLT_UNRECOGNIZED_DRAM_DEVICE_TYPE</rc> - <description>Unsupported DIMM type found. All dimms must be DDR3 or DDR4</description> - <ffdc>DEVICE_TYPE</ffdc> - <callout> - <target>DIMM_TARGET</target> - <priority>HIGH</priority> - </callout> - <deconfigure> - <target>DIMM_TARGET</target> - </deconfigure> - </hwpError> - -<!-- Original Source for RC_MSS_VOLT_DDR_TYPE_MIXING_UNSUPPORTED memory_errors.xml --> - <hwpError> - <rc>RC_MSS_VOLT_DDR_TYPE_MIXING_UNSUPPORTED</rc> - <description>Mixing of DDR3 and DDR4 not supported.</description> - <ffdc>DEVICE_TYPE</ffdc> - <callout> - <target>DIMM_DDR4_TARGET</target> - <priority>HIGH</priority> - </callout> - <deconfigure> - <target>DIMM_DDR4_TARGET</target> - </deconfigure> - </hwpError> - -<!-- Original Source for RC_MSS_VOLT_DDR_TYPE_REQUIRED_VOLTAGE memory_errors.xml --> <hwpError> <rc>RC_MSS_VOLT_DDR_TYPE_REQUIRED_VOLTAGE</rc> <description>One or more DIMMs do not support required voltage for DDR type.</description> - <ffdc>OPERABLE</ffdc> - <ffdc>ENDURANT</ffdc> + <ffdc>EXPECTED_OPERABLE</ffdc> + <ffdc>EXPECTED_ENDURANT</ffdc> + <ffdc>ACTUAL_OPERABLE</ffdc> + <ffdc>ACTUAL_ENDURANT</ffdc> + <callout> + <procedure>MEMORY_PLUGGING_ERROR</procedure> + <priority>HIGH</priority> + </callout> <callout> <target>DIMM_TARGET</target> - <priority>HIGH</priority> + <priority>MEDIUM</priority> </callout> <deconfigure> <target>DIMM_TARGET</target> </deconfigure> </hwpError> - -<!-- Original Source for RC_MSS_VOLT_TOLERATED_VOLTAGE_VIOLATION memory_errors.xml --> - <hwpError> - <rc>RC_MSS_VOLT_TOLERATED_VOLTAGE_VIOLATION</rc> - <description>One or more DIMMs classified non-functional has a tolerated voltage below selected voltage.</description> - <ffdc>DIMM_VOLTAGE</ffdc> - <!-- Deconfigure DIMM or Centaur --> - <deconfigure> - <target>CHIP_TARGET</target> - </deconfigure> - </hwpError> - - <hwpError> - <rc>RC_MSS_VOLT_OVERIDE_MIXING</rc> - <description>An override is trying to be applied to only a part of the voltage domain. It needs to be applied to the entire domain.</description> - <ffdc>OVERRIDE_TYPE</ffdc> - <ffdc>OVERRIDE_DOMAIN_TYPE</ffdc> - <callout> - <target>MEMB_TARGET</target> - <priority>HIGH</priority> - </callout> - </hwpError> - - <hwpError> - <rc>RC_MSS_VOLT_OVERIDE_UKNOWN</rc> - <description>An uknown override is trying to be applied to the voltage domain. It needs to be none, 1.2 or 1.35V. </description> - <ffdc>OVERRIDE_TYPE</ffdc> - <callout> - <procedure>CODE</procedure> - <priority>HIGH</priority> - </callout> - </hwpError> - </hwpErrors> diff --git a/src/import/chips/p9/procedures/xml/error_info/p9_mss_attr_update_errors.xml b/src/import/chips/p9/procedures/xml/error_info/p9_mss_attr_update_errors.xml index a84229d0d..a782e8df9 100644 --- a/src/import/chips/p9/procedures/xml/error_info/p9_mss_attr_update_errors.xml +++ b/src/import/chips/p9/procedures/xml/error_info/p9_mss_attr_update_errors.xml @@ -31,8 +31,15 @@ Procedure: p9_mss_attr_update Unsupported MVPD CRP0 Lx Keyword version </description> - <ffdc>TARGET</ffdc> + <ffdc>CHIP_TARGET</ffdc> <ffdc>VERSION</ffdc> + <callout> + <hw> + <hwid>VPD_PART</hwid> + <refTarget>CHIP_TARGET</refTarget> + </hw> + <priority>HIGH</priority> + </callout> </hwpError> <!-- ******************************************************************** --> <hwpError> @@ -41,8 +48,15 @@ Procedure: p9_mss_attr_update Unexpected MVPD CRP0 Lx Keyword size </description> - <ffdc>TARGET</ffdc> + <ffdc>CHIP_TARGET</ffdc> <ffdc>KEYWORD_SIZE</ffdc> + <callout> + <hw> + <hwid>VPD_PART</hwid> + <refTarget>CHIP_TARGET</refTarget> + </hw> + <priority>HIGH</priority> + </callout> </hwpError> <!-- ******************************************************************** --> </hwpErrors> |