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author | Stephen Glancy <sglancy@us.ibm.com> | 2018-11-09 12:01:21 -0600 |
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committer | Christian R. Geddes <crgeddes@us.ibm.com> | 2018-11-21 15:58:41 -0600 |
commit | 14dbbd68d03d2447254d21ad6426e472d102a817 (patch) | |
tree | c33b6e0e12951f0b046598adda0c218db0c89ec6 /src/import/chips/p9 | |
parent | 25b23bbf30865d5bc46db6ab22d4ebb2fdd472ee (diff) | |
download | talos-hostboot-14dbbd68d03d2447254d21ad6426e472d102a817.tar.gz talos-hostboot-14dbbd68d03d2447254d21ad6426e472d102a817.zip |
Fixes set_pba_mode to use proper F0BC1x values
Change-Id: I51438d3f84364b2bbec02a58058b5b6fba0758a7
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/68599
Reviewed-by: Louis Stermole <stermole@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: ANDRE A. MARIN <aamarin@us.ibm.com>
Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/68602
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>
Diffstat (limited to 'src/import/chips/p9')
-rw-r--r-- | src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/data_buffer_ddr4.H | 29 | ||||
-rw-r--r-- | src/import/chips/p9/procedures/hwp/memory/lib/shared/mss_const.H | 1 |
2 files changed, 21 insertions, 9 deletions
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/data_buffer_ddr4.H b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/data_buffer_ddr4.H index ab980a962..05b1f2f2d 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/data_buffer_ddr4.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/data_buffer_ddr4.H @@ -473,20 +473,31 @@ inline fapi2::ReturnCode set_pba_mode( const fapi2::Target<fapi2::TARGET_TYPE_DI const mss::states i_state, std::vector< ccs::instruction_t<T> >& io_inst ) { + // PBA position is really bit 0, but we're right justified on our bit ordering here, so it's bit7 + constexpr uint64_t PBA_POSITION = 7; constexpr uint64_t MAX_VALID = 1; + uint8_t l_nominal_bc_value = 0; + + // Error checking + FAPI_ASSERT(i_state <= MAX_VALID, + fapi2::MSS_OUT_OF_BOUNDS_INDEXING() + .set_TARGET(i_target) + .set_INDEX(i_state) + .set_LIST_SIZE(MAX_VALID) + .set_FUNCTION(SET_PBA_MODE), + "%s has PBA input (%u) out of bounds: %u", + mss::c_str(i_target), i_state, MAX_VALID); + + // Gets our nominal BCW value + FAPI_TRY(mss::eff_dimm_ddr4_f0bc1x(i_target, l_nominal_bc_value)); - // User input programming error asserts program termination - if( i_state > MAX_VALID ) { - FAPI_ERR( "%s. Invalid setting received: %d, largest valid PBA setting is %d", - mss::c_str(i_target), i_state, MAX_VALID ); - fapi2::Assert(false); + cw_data l_data(FUNC_SPACE_0, BUFF_CONFIG_CW, l_nominal_bc_value, mss::tmrc()); + l_data.iv_data.writeBit<PBA_POSITION>(i_state); + FAPI_INF("%s data 0x%02x", mss::c_str(i_target), l_data.iv_data); + FAPI_TRY( settings_boilerplate<BCW_8BIT>(i_target, l_data, io_inst) ); } - cw_data l_data(FUNC_SPACE_0, BUFF_CONFIG_CW, i_state, mss::tmrc()); - FAPI_INF("%s data 0x%02x", mss::c_str(i_target), l_data.iv_data); - FAPI_TRY( settings_boilerplate<BCW_8BIT>(i_target, l_data, io_inst) ); - fapi_try_exit: return fapi2::current_err; } diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/shared/mss_const.H b/src/import/chips/p9/procedures/hwp/memory/lib/shared/mss_const.H index 7676d5f3f..d1effb898 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/shared/mss_const.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/shared/mss_const.H @@ -203,6 +203,7 @@ enum ffdc_function_codes // PBA function codes PBA_EXECUTE_CONTAINER = 80, PBA_EXECUTE_VECTOR = 81, + SET_PBA_MODE = 83, }; enum states |