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author | Brian Silver <bsilver@us.ibm.com> | 2016-03-08 14:34:09 -0600 |
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committer | Daniel M. Crowell <dcrowell@us.ibm.com> | 2016-03-22 17:25:40 -0400 |
commit | 8acb41d0016e2e85dd464dfb383bedf63a53e4de (patch) | |
tree | d7bf4b5c0c4337f0a7c270c1063145ea4c0cf363 /src/import/chips/p9 | |
parent | 5dbc0fbe5ef62a1e11306ba37dcc8fd818a4b767 (diff) | |
download | talos-hostboot-8acb41d0016e2e85dd464dfb383bedf63a53e4de.tar.gz talos-hostboot-8acb41d0016e2e85dd464dfb383bedf63a53e4de.zip |
Change comments, return code for mcbist 2 port testing
Change-Id: I1d45e9a62b39397bc33c357506f158665cc77347
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/22339
Tested-by: Jenkins Server
Tested-by: Hostboot CI
Reviewed-by: Louis Stermole <stermole@us.ibm.com>
Reviewed-by: ANDRE A. MARIN <aamarin@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/22340
Tested-by: FSP CI Jenkins
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Diffstat (limited to 'src/import/chips/p9')
-rw-r--r-- | src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit_mc.C | 4 |
1 files changed, 1 insertions, 3 deletions
diff --git a/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit_mc.C b/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit_mc.C index 4cfee8edd..78ba0b143 100644 --- a/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit_mc.C +++ b/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit_mc.C @@ -91,9 +91,7 @@ extern "C" // Reset addr_mux_sel to “0” to allow the MCA to take control of the DDR interface over from CCS. // (Note: this step must remain in this procedure to ensure that data path is placed into mainline - // mode prior to running memory diagnostics. When Advanced DRAM Training executes, this step - // becomes superfluous but not harmful. However, it's not guaranteed that Advanced DRAM Training - // will be executed on every system configuration.) + // mode prior to running memory diagnostics. This step maybe superfluous but not harmful.) // Note: addr_mux_sel is set low in p9_mss_draminit(), however that might be a work-around so we // set it low here kind of like belt-and-suspenders. BRS FAPI_TRY( mss::change_addr_mux_sel(p, mss::LOW) ); |