Restore original training settings if mss_draminit_training_adv fails

Change-Id: I5bb98825c38c867fc2d9a41dd15537f3d55fbe88
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/46412
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Reviewed-by: JACOB L. HARVEY <jlharvey@us.ibm.com>
Reviewed-by: STEPHEN GLANCY <sglancy@us.ibm.com>
Reviewed-by: ANDRE A. MARIN <aamarin@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/46416
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>

3 files changed, 627 insertions, 32 deletions

diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/phy/dp16.C b/src/import/chips/p9/procedures/hwp/memory/lib/phy/dp16.C
index 05a7ff902..0e346881a 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/phy/dp16.C
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/phy/dp16.C
@@ -619,6 +619,449 @@ const std::vector< uint64_t > dp16Traits<TARGET_TYPE_MCA>::WR_ERROR0_REG =
     MCA_DDRPHY_DP16_WR_ERROR0_P0_4,
 };
 
+// Definition of the READ_DELAY registers, per rank pair
+const std::vector< std::vector<uint64_t> > dp16Traits<TARGET_TYPE_MCA>::READ_DELAY_REG =
+{
+    {
+        MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR0_P0_0,
+        MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR0_P0_0,
+        MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR0_P0_0,
+        MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR0_P0_0,
+        MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR0_P0_0,
+        MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR0_P0_0,
+        MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR0_P0_0,
+        MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR0_P0_0,
+        MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR0_P0_1,
+        MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR0_P0_1,
+        MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR0_P0_1,
+        MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR0_P0_1,
+        MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR0_P0_1,
+        MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR0_P0_1,
+        MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR0_P0_1,
+        MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR0_P0_1,
+        MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR0_P0_2,
+        MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR0_P0_2,
+        MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR0_P0_2,
+        MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR0_P0_2,
+        MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR0_P0_2,
+        MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR0_P0_2,
+        MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR0_P0_2,
+        MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR0_P0_2,
+        MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR0_P0_3,
+        MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR0_P0_3,
+        MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR0_P0_3,
+        MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR0_P0_3,
+        MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR0_P0_3,
+        MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR0_P0_3,
+        MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR0_P0_3,
+        MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR0_P0_3,
+        MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR0_P0_4,
+        MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR0_P0_4,
+        MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR0_P0_4,
+        MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR0_P0_4,
+    },
+    {
+        MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR1_P0_0,
+        MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR1_P0_0,
+        MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR1_P0_0,
+        MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR1_P0_0,
+        MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR1_P0_0,
+        MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR1_P0_0,
+        MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR1_P0_0,
+        MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR1_P0_0,
+        MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR1_P0_1,
+        MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR1_P0_1,
+        MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR1_P0_1,
+        MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR1_P0_1,
+        MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR1_P0_1,
+        MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR1_P0_1,
+        MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR1_P0_1,
+        MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR1_P0_1,
+        MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR1_P0_2,
+        MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR1_P0_2,
+        MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR1_P0_2,
+        MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR1_P0_2,
+        MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR1_P0_2,
+        MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR1_P0_2,
+        MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR1_P0_2,
+        MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR1_P0_2,
+        MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR1_P0_3,
+        MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR1_P0_3,
+        MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR1_P0_3,
+        MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR1_P0_3,
+        MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR1_P0_3,
+        MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR1_P0_3,
+        MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR1_P0_3,
+        MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR1_P0_3,
+        MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR1_P0_4,
+        MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR1_P0_4,
+        MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR1_P0_4,
+        MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR1_P0_4,
+    },
+    {
+        MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR2_P0_0,
+        MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR2_P0_0,
+        MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR2_P0_0,
+        MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR2_P0_0,
+        MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR2_P0_0,
+        MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR2_P0_0,
+        MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR2_P0_0,
+        MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR2_P0_0,
+        MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR2_P0_1,
+        MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR2_P0_1,
+        MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR2_P0_1,
+        MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR2_P0_1,
+        MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR2_P0_1,
+        MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR2_P0_1,
+        MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR2_P0_1,
+        MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR2_P0_1,
+        MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR2_P0_2,
+        MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR2_P0_2,
+        MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR2_P0_2,
+        MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR2_P0_2,
+        MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR2_P0_2,
+        MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR2_P0_2,
+        MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR2_P0_2,
+        MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR2_P0_2,
+        MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR2_P0_3,
+        MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR2_P0_3,
+        MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR2_P0_3,
+        MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR2_P0_3,
+        MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR2_P0_3,
+        MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR2_P0_3,
+        MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR2_P0_3,
+        MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR2_P0_3,
+        MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR2_P0_4,
+        MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR2_P0_4,
+        MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR2_P0_4,
+        MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR2_P0_4,
+    },
+    {
+        MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR3_P0_0,
+        MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR3_P0_0,
+        MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR3_P0_0,
+        MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR3_P0_0,
+        MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR3_P0_0,
+        MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR3_P0_0,
+        MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR3_P0_0,
+        MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR3_P0_0,
+        MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR3_P0_1,
+        MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR3_P0_1,
+        MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR3_P0_1,
+        MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR3_P0_1,
+        MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR3_P0_1,
+        MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR3_P0_1,
+        MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR3_P0_1,
+        MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR3_P0_1,
+        MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR3_P0_2,
+        MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR3_P0_2,
+        MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR3_P0_2,
+        MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR3_P0_2,
+        MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR3_P0_2,
+        MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR3_P0_2,
+        MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR3_P0_2,
+        MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR3_P0_2,
+        MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR3_P0_3,
+        MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR3_P0_3,
+        MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR3_P0_3,
+        MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR3_P0_3,
+        MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR3_P0_3,
+        MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR3_P0_3,
+        MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR3_P0_3,
+        MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR3_P0_3,
+        MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR3_P0_4,
+        MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR3_P0_4,
+        MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR3_P0_4,
+        MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR3_P0_4,
+    },
+};
+
+// Definition of the READ_EYE_SIZE registers, per rank pair
+const std::vector< std::vector<uint64_t> > dp16Traits<TARGET_TYPE_MCA>::READ_EYE_SIZE_REG =
+{
+    {
+        MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR0_P0_0,
+        MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR0_P0_0,
+        MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR0_P0_0,
+        MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR0_P0_0,
+        MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR0_P0_0,
+        MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR0_P0_0,
+        MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR0_P0_0,
+        MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR0_P0_0,
+        MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR0_P0_0,
+        MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR0_P0_0,
+        MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR0_P0_0,
+        MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR0_P0_0,
+        MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR0_P0_1,
+        MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR0_P0_1,
+        MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR0_P0_1,
+        MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR0_P0_1,
+        MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR0_P0_1,
+        MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR0_P0_1,
+        MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR0_P0_1,
+        MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR0_P0_1,
+        MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR0_P0_1,
+        MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR0_P0_1,
+        MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR0_P0_1,
+        MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR0_P0_1,
+        MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR0_P0_2,
+        MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR0_P0_2,
+        MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR0_P0_2,
+        MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR0_P0_2,
+        MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR0_P0_2,
+        MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR0_P0_2,
+        MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR0_P0_2,
+        MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR0_P0_2,
+        MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR0_P0_2,
+        MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR0_P0_2,
+        MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR0_P0_2,
+        MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR0_P0_2,
+        MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR0_P0_3,
+        MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR0_P0_3,
+        MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR0_P0_3,
+        MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR0_P0_3,
+        MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR0_P0_3,
+        MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR0_P0_3,
+        MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR0_P0_3,
+        MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR0_P0_3,
+        MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR0_P0_3,
+        MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR0_P0_3,
+        MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR0_P0_3,
+        MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR0_P0_3,
+        MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR0_P0_4,
+        MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR0_P0_4,
+        MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR0_P0_4,
+        MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR0_P0_4,
+        MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR0_P0_4,
+        MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR0_P0_4,
+        MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR0_P0_4,
+        MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR0_P0_4,
+        MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR0_P0_4,
+        MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR0_P0_4,
+        MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR0_P0_4,
+        MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR0_P0_4,
+    },
+    {
+        MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR1_P0_0,
+        MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR1_P0_0,
+        MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR1_P0_0,
+        MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR1_P0_0,
+        MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR1_P0_0,
+        MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR1_P0_0,
+        MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR1_P0_0,
+        MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR1_P0_0,
+        MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR1_P0_0,
+        MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR1_P0_0,
+        MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR1_P0_0,
+        MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR1_P0_0,
+        MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR1_P0_1,
+        MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR1_P0_1,
+        MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR1_P0_1,
+        MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR1_P0_1,
+        MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR1_P0_1,
+        MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR1_P0_1,
+        MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR1_P0_1,
+        MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR1_P0_1,
+        MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR1_P0_1,
+        MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR1_P0_1,
+        MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR1_P0_1,
+        MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR1_P0_1,
+        MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR1_P0_2,
+        MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR1_P0_2,
+        MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR1_P0_2,
+        MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR1_P0_2,
+        MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR1_P0_2,
+        MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR1_P0_2,
+        MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR1_P0_2,
+        MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR1_P0_2,
+        MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR1_P0_2,
+        MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR1_P0_2,
+        MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR1_P0_2,
+        MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR1_P0_2,
+        MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR1_P0_3,
+        MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR1_P0_3,
+        MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR1_P0_3,
+        MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR1_P0_3,
+        MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR1_P0_3,
+        MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR1_P0_3,
+        MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR1_P0_3,
+        MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR1_P0_3,
+        MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR1_P0_3,
+        MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR1_P0_3,
+        MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR1_P0_3,
+        MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR1_P0_3,
+        MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR1_P0_4,
+        MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR1_P0_4,
+        MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR1_P0_4,
+        MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR1_P0_4,
+        MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR1_P0_4,
+        MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR1_P0_4,
+        MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR1_P0_4,
+        MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR1_P0_4,
+        MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR1_P0_4,
+        MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR1_P0_4,
+        MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR1_P0_4,
+        MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR1_P0_4,
+    },
+    {
+        MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR2_P0_0,
+        MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR2_P0_0,
+        MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR2_P0_0,
+        MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR2_P0_0,
+        MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR2_P0_0,
+        MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR2_P0_0,
+        MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR2_P0_0,
+        MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR2_P0_0,
+        MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR2_P0_0,
+        MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR2_P0_0,
+        MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR2_P0_0,
+        MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR2_P0_0,
+        MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR2_P0_1,
+        MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR2_P0_1,
+        MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR2_P0_1,
+        MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR2_P0_1,
+        MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR2_P0_1,
+        MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR2_P0_1,
+        MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR2_P0_1,
+        MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR2_P0_1,
+        MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR2_P0_1,
+        MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR2_P0_1,
+        MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR2_P0_1,
+        MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR2_P0_1,
+        MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR2_P0_2,
+        MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR2_P0_2,
+        MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR2_P0_2,
+        MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR2_P0_2,
+        MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR2_P0_2,
+        MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR2_P0_2,
+        MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR2_P0_2,
+        MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR2_P0_2,
+        MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR2_P0_2,
+        MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR2_P0_2,
+        MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR2_P0_2,
+        MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR2_P0_2,
+        MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR2_P0_3,
+        MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR2_P0_3,
+        MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR2_P0_3,
+        MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR2_P0_3,
+        MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR2_P0_3,
+        MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR2_P0_3,
+        MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR2_P0_3,
+        MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR2_P0_3,
+        MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR2_P0_3,
+        MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR2_P0_3,
+        MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR2_P0_3,
+        MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR2_P0_3,
+        MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR2_P0_4,
+        MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR2_P0_4,
+        MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR2_P0_4,
+        MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR2_P0_4,
+        MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR2_P0_4,
+        MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR2_P0_4,
+        MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR2_P0_4,
+        MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR2_P0_4,
+        MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR2_P0_4,
+        MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR2_P0_4,
+        MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR2_P0_4,
+        MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR2_P0_4,
+    },
+    {
+        MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR3_P0_0,
+        MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR3_P0_0,
+        MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR3_P0_0,
+        MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR3_P0_0,
+        MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR3_P0_0,
+        MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR3_P0_0,
+        MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR3_P0_0,
+        MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR3_P0_0,
+        MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR3_P0_0,
+        MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR3_P0_0,
+        MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR3_P0_0,
+        MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR3_P0_0,
+        MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR3_P0_1,
+        MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR3_P0_1,
+        MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR3_P0_1,
+        MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR3_P0_1,
+        MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR3_P0_1,
+        MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR3_P0_1,
+        MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR3_P0_1,
+        MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR3_P0_1,
+        MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR3_P0_1,
+        MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR3_P0_1,
+        MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR3_P0_1,
+        MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR3_P0_1,
+        MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR3_P0_2,
+        MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR3_P0_2,
+        MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR3_P0_2,
+        MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR3_P0_2,
+        MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR3_P0_2,
+        MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR3_P0_2,
+        MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR3_P0_2,
+        MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR3_P0_2,
+        MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR3_P0_2,
+        MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR3_P0_2,
+        MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR3_P0_2,
+        MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR3_P0_2,
+        MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR3_P0_3,
+        MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR3_P0_3,
+        MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR3_P0_3,
+        MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR3_P0_3,
+        MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR3_P0_3,
+        MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR3_P0_3,
+        MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR3_P0_3,
+        MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR3_P0_3,
+        MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR3_P0_3,
+        MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR3_P0_3,
+        MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR3_P0_3,
+        MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR3_P0_3,
+        MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR3_P0_4,
+        MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR3_P0_4,
+        MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR3_P0_4,
+        MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR3_P0_4,
+        MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR3_P0_4,
+        MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR3_P0_4,
+        MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR3_P0_4,
+        MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR3_P0_4,
+        MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR3_P0_4,
+        MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR3_P0_4,
+        MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR3_P0_4,
+        MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR3_P0_4,
+    },
+};
+
+// Definition of the RDCLK delay registers, per rank pair
+const std::vector< std::vector<uint64_t> > dp16Traits<TARGET_TYPE_MCA>::RDCLK_REG =
+{
+    {
+        MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_0,
+        MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_1,
+        MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_2,
+        MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_3,
+        MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_4,
+    },
+    {
+        MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_0,
+        MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_1,
+        MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_2,
+        MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_3,
+        MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_4,
+    },
+    {
+        MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_0,
+        MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_1,
+        MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_2,
+        MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_3,
+        MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_4,
+    },
+    {
+        MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_0,
+        MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_1,
+        MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_2,
+        MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_3,
+        MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_4,
+    },
+};
+
 ///
 /// @brief Given a RD_VREF value, create a PHY 'standard' bit field for that percentage.
 /// @tparam T fapi2 Target Type - derived
@@ -940,6 +1383,124 @@ static const register_data_vector rdclk_enable_spare_x4[] =
 };
 
 ///
+/// @brief Save settings for a given rank pair
+/// @return FAPI2_RC_SUCCES iff ok
+///
+template<>
+fapi2::ReturnCode rd_ctr_settings<TARGET_TYPE_MCA>::save()
+{
+    typedef mss::dp16Traits<TARGET_TYPE_MCA> TT;
+
+    // Read each register and save in private variables
+    FAPI_TRY( mss::scom_suckah(iv_target, TT::READ_DELAY_REG[iv_rp], iv_read_delay) );
+    FAPI_TRY( mss::scom_suckah(iv_target, TT::RDCLK_REG[iv_rp], iv_rdclk_delay) );
+    FAPI_TRY( mss::scom_suckah(iv_target, TT::BIT_DISABLE_REG[iv_rp], iv_dq_disable) );
+    FAPI_TRY( mss::scom_suckah(iv_target, TT::READ_EYE_SIZE_REG[iv_rp], iv_read_eye_size) );
+
+fapi_try_exit:
+    return fapi2::current_err;
+}
+
+///
+/// @brief Restore settings for a given rank pair
+/// @return FAPI2_RC_SUCCES iff ok
+///
+template<>
+fapi2::ReturnCode rd_ctr_settings<TARGET_TYPE_MCA>::restore()
+{
+    typedef mss::dp16Traits<TARGET_TYPE_MCA> TT;
+
+    std::vector<fapi2::buffer<uint64_t>> l_post_training_settings;
+    std::vector<std::pair<fapi2::buffer<uint64_t>, fapi2::buffer<uint64_t> > > l_post_training_disables;
+
+    // Log values before restoring them
+    FAPI_TRY( mss::scom_suckah(iv_target, TT::READ_DELAY_REG[iv_rp], l_post_training_settings) );
+
+    if( l_post_training_settings.size() != iv_read_delay.size() )
+    {
+        // Asserting out instead of collecting FFDC since this is a
+        // programming bug that shouldn't occur.
+        FAPI_ERR("Number of READ_DELAY registers != number of stored registers: %d != %d",
+                 l_post_training_settings.size(), iv_read_delay.size());
+        fapi2::Assert(false);
+    }
+
+    // TK Should these messages be written in FFDC so we can see them in FW?
+    for (uint64_t l_idx = 0; l_idx < l_post_training_settings.size(); ++l_idx)
+    {
+        FAPI_INF("%s restoring value of READ_DELAY scom 0x%016llx from 0x%016llx to 0x%016llx",
+                 mss::c_str(iv_target), TT::READ_DELAY_REG[iv_rp][l_idx], l_post_training_settings[l_idx], iv_read_delay[l_idx]);
+    }
+
+    FAPI_TRY( mss::scom_suckah(iv_target, TT::RDCLK_REG[iv_rp], l_post_training_settings) );
+
+    if( l_post_training_settings.size() != iv_rdclk_delay.size() )
+    {
+        // Asserting out instead of collecting FFDC since this is a
+        // programming bug that shouldn't occur.
+        FAPI_ERR("Number of RDCLK registers != number of stored registers: %d != %d",
+                 l_post_training_settings.size(), iv_rdclk_delay.size());
+        fapi2::Assert(false);
+    }
+
+    for (uint64_t l_idx = 0; l_idx < l_post_training_settings.size(); ++l_idx)
+    {
+        FAPI_INF("%s restoring value of RDCLK scom 0x%016llx from 0x%016llx to 0x%016llx",
+                 mss::c_str(iv_target), TT::RDCLK_REG[iv_rp][l_idx], l_post_training_settings[l_idx], iv_rdclk_delay[l_idx]);
+    }
+
+    FAPI_TRY( mss::scom_suckah(iv_target, TT::BIT_DISABLE_REG[iv_rp], l_post_training_disables) );
+
+    if( l_post_training_disables.size() != iv_dq_disable.size() )
+    {
+        // Asserting out instead of collecting FFDC since this is a
+        // programming bug that shouldn't occur.
+        FAPI_ERR("Number of BIT_DISABLE registers != number of stored registers: %d != %d",
+                 l_post_training_disables.size(), iv_dq_disable.size());
+        fapi2::Assert(false);
+    }
+
+    for (uint64_t l_idx = 0; l_idx < l_post_training_disables.size(); ++l_idx)
+    {
+        FAPI_INF("%s restoring value of DATA_DISABLE scom 0x%016llx from 0x%016llx to 0x%016llx",
+                 mss::c_str(iv_target), TT::BIT_DISABLE_REG[iv_rp][l_idx].first, l_post_training_disables[l_idx].first,
+                 iv_dq_disable[l_idx].first);
+        FAPI_INF("%s restoring value of DATA_DISABLE scom 0x%016llx from 0x%016llx to 0x%016llx",
+                 mss::c_str(iv_target), TT::BIT_DISABLE_REG[iv_rp][l_idx].second, l_post_training_disables[l_idx].second,
+                 iv_dq_disable[l_idx].second);
+    }
+
+    FAPI_TRY( mss::scom_suckah(iv_target, TT::READ_EYE_SIZE_REG[iv_rp], l_post_training_settings) );
+
+    if( l_post_training_settings.size() != iv_read_eye_size.size() )
+    {
+        // Asserting out instead of collecting FFDC since this is a
+        // programming bug that shouldn't occur.
+        FAPI_ERR("Number of READ_EYE_SIZE registers != number of stored registers: %d != %d",
+                 l_post_training_settings.size(), iv_read_eye_size.size());
+        fapi2::Assert(false);
+    }
+
+    for (uint64_t l_idx = 0; l_idx < l_post_training_settings.size(); ++l_idx)
+    {
+        FAPI_INF("%s restoring value of READ_EYE_SIZE scom 0x%016llx from 0x%016llx to 0x%016llx",
+                 mss::c_str(iv_target), TT::READ_EYE_SIZE_REG[iv_rp][l_idx], l_post_training_settings[l_idx], iv_read_eye_size[l_idx]);
+    }
+
+    // Write each register back from private variables
+    FAPI_TRY( mss::scom_blastah(iv_target, TT::READ_DELAY_REG[iv_rp], iv_read_delay) );
+    FAPI_TRY( mss::scom_blastah(iv_target, TT::RDCLK_REG[iv_rp], iv_rdclk_delay) );
+    FAPI_TRY( mss::scom_blastah(iv_target, TT::BIT_DISABLE_REG[iv_rp], iv_dq_disable) );
+    FAPI_TRY( mss::scom_blastah(iv_target, TT::READ_EYE_SIZE_REG[iv_rp], iv_read_eye_size) );
+
+    // Run the record_bad_bits function to restore the BAD_DQ_BITMAP attribute using the pre-training disable bits
+    FAPI_TRY( mss::dp16::record_bad_bits(iv_target) );
+
+fapi_try_exit:
+    return fapi2::current_err;
+}
+
+///
 /// @brief Reset the data bit enable registers
 /// @param[in] i_target  a port target
 /// @return FAPI2_RC_SUCCES iff ok
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/phy/dp16.H b/src/import/chips/p9/procedures/hwp/memory/lib/phy/dp16.H
index e785f7d00..7f79078d3 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/phy/dp16.H
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/phy/dp16.H
@@ -223,6 +223,15 @@ class dp16Traits<fapi2::TARGET_TYPE_MCA>
             MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_0_01_RDCLK_SELECT3,
         };
 
+        // READ_DELAY registers, indexed by rank_pair
+        static const std::vector< std::vector< uint64_t > > READ_DELAY_REG;
+
+        // READ_EYE_SIZE registers, indexed by rank_pair
+        static const std::vector< std::vector< uint64_t > > READ_EYE_SIZE_REG;
+
+        // RDCLK delay registers, indexed by rank_pair
+        static const std::vector< std::vector< uint64_t > > RDCLK_REG;
+
         enum
         {
             // Name changes for dd2 to P9N2_MCA_DDRPHY_DP16_RX_CONFIG0_P0_0
@@ -393,6 +402,48 @@ namespace dp16
 {
 
 ///
+/// @class rd_ctr_settings
+/// @brief Stores pre-training_adv RD_CTR PHY settings, so they can be restored if training_adv fails
+/// @tparam T target type representing a port
+///
+template< fapi2::TargetType T >
+class rd_ctr_settings
+{
+    public:
+        rd_ctr_settings() = delete;
+
+        ///
+        /// @brief rd_ctr_settings constructor
+        /// @param[in] i_target the port target
+        /// @param[in] i_rp the rank pair
+        ///
+        rd_ctr_settings( const fapi2::Target<T>& i_target, const uint64_t i_rp ):
+            iv_target(i_target), iv_rp(i_rp)
+        {
+        }
+
+        ///
+        /// @brief Save settings for a given rank pair
+        /// @return FAPI2_RC_SUCCES iff ok
+        ///
+        fapi2::ReturnCode save();
+
+        ///
+        /// @brief Restore settings for a given rank pair
+        /// @return FAPI2_RC_SUCCES iff ok
+        ///
+        fapi2::ReturnCode restore();
+
+    private:
+        const fapi2::Target<T> iv_target;
+        const uint64_t iv_rp;
+        std::vector<fapi2::buffer<uint64_t>> iv_read_delay;
+        std::vector<fapi2::buffer<uint64_t>> iv_rdclk_delay;
+        std::vector<std::pair<fapi2::buffer<uint64_t>, fapi2::buffer<uint64_t> > > iv_dq_disable;
+        std::vector<fapi2::buffer<uint64_t>> iv_read_eye_size;
+};
+
+///
 /// @brief Read TSYS_DATA
 /// @tparam I DP16 instance
 /// @tparam T fapi2 Target Type - derived
diff --git a/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit_training_adv.C b/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit_training_adv.C
index 98df4c3c0..35ccf81fb 100644
--- a/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit_training_adv.C
+++ b/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit_training_adv.C
@@ -59,7 +59,6 @@ extern "C"
     fapi2::ReturnCode p9_mss_draminit_training_adv( const fapi2::Target<TARGET_TYPE_MCBIST>& i_target,
             const uint8_t i_abort_on_error)
     {
-        std::vector<fapi2::ReturnCode> l_fails;
         uint8_t l_cal_abort_on_error = i_abort_on_error;
         uint8_t l_sim = 0;
         FAPI_TRY( mss::is_simulation (l_sim) );
@@ -134,17 +133,19 @@ extern "C"
             {
                 bool l_cal_fail = false;
 
-                // l_fails is used to see if we need to rerun training.
-                // The other vector, l_fails, will be used to store errors across all of the ports
-                std::vector<fapi2::ReturnCode> l_temp_fails;
+                // Save off registers in case adv training fails
+                mss::dp16::rd_ctr_settings<TARGET_TYPE_MCA> l_original_settings(p, rp);
+                FAPI_TRY( l_original_settings.save() );
 
+                std::vector<fapi2::ReturnCode> l_fails_on_rp;
                 FAPI_TRY( mss::setup_and_execute_cal(p, rp, l_cal_steps_enabled, l_cal_abort_on_error) );
-                FAPI_TRY( mss::find_and_log_cal_errors(p, rp, l_cal_abort_on_error, l_cal_fail, l_temp_fails) );
+                FAPI_TRY( mss::find_and_log_cal_errors(p, rp, l_cal_abort_on_error, l_cal_fail, l_fails_on_rp) );
 
                 // If we got a fail, let's ignore the previous fails and run backup pattern
-                if (l_temp_fails.size() != 0)
+                if (l_fails_on_rp.size() != 0)
                 {
                     l_cal_fail = false;
+                    l_fails_on_rp.clear();
 
                     // Clear the disable bits from last run.
                     // This function restores bad_bits to how the attribute has them
@@ -164,27 +165,16 @@ extern "C"
 
                     // Rerun the training for this rp
                     FAPI_TRY( mss::setup_and_execute_cal(p, rp, l_cal_steps_enabled, l_cal_abort_on_error) );
-                    FAPI_TRY( mss::find_and_log_cal_errors(p, rp, l_cal_abort_on_error, l_cal_fail, l_fails) );
+                    FAPI_TRY( mss::find_and_log_cal_errors(p, rp, l_cal_abort_on_error, l_cal_fail, l_fails_on_rp) );
 
-                    // Fail out for now.
-                    // TK should restore values here
-                    if (l_fails.size() != 0)
+                    // If we got fails from the backup pattern, restore the pre-adv training settings for this rank pair
+                    if (l_fails_on_rp.size() != 0)
                     {
-                        fapi2::Target<fapi2::TARGET_TYPE_DIMM> l_dimm;
-
-                        // Let's get the DIMM since we train per rank pair (primary rank pair)
-                        FAPI_TRY( mss::rank_pair_primary_to_dimm(p,
-                                  rp,
-                                  l_dimm),
-                                  "Failed getting the DIMM for %s rp %x", mss::c_str(p), rp);
-
-                        FAPI_ASSERT( l_cal_fail == false,
-                                     fapi2::MSS_DRAMINIT_TRAINING_CUSTOM_PATTERN_RD_ERROR()
-                                     .set_PORT_POSITION(mss::index(p))
-                                     .set_RANKGROUP_POSITION(rp)
-                                     .set_MCA_TARGET(p)
-                                     .set_DIMM_TARGET(l_dimm),
-                                     "%s rp%x Failed Draminit_training_adv", mss::c_str(p), rp);
+                        l_fails_on_rp.clear();
+                        FAPI_INF("%s rp%d draminit_training_adv failed. Restoring original settings", mss::c_str(p), rp);
+
+                        // Restore pre-training_adv settings
+                        FAPI_TRY( l_original_settings.restore() );
                     }
                 }
             }// rank pairs
@@ -194,13 +184,6 @@ extern "C"
             fapi2::current_err = fapi2::FAPI2_RC_SUCCESS;
         }
 
-        // If we fail draminit_training_adv, we should exit out the ipl / reconfigure
-        // Shouldn't really get here but let's do it anyways
-        if (l_fails.size() != 0)
-        {
-            FAPI_TRY(l_fails[0]);
-        }
-
         return fapi2::FAPI2_RC_SUCCESS;
     fapi_try_exit:
         return fapi2::current_err;