Enable skipping sbefifo reset during p9_start_cbs

 For certain systems (RBI/WAFER) under Cronus
 skip resetting the sbefifo via cfam register
 as it is not available on those FSPs. Use a
 new attribute to determine if it is correct
 to skip this cfam register write.

Change-Id: I9f63e042f7a3a17b6f7f4c52cd2b4cdf9f2d4aa9
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/42811
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Joachim Fenkes <fenkes@de.ibm.com>
Reviewed-by: SRINIVAS V. POLISETTY <srinivan@in.ibm.com>
Dev-Ready: Matt K. Light <mklight@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/42815
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>

3 files changed, 41 insertions, 2 deletions

diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/mss_attribute_accessors.H b/src/import/chips/p9/procedures/hwp/memory/lib/mss_attribute_accessors.H
index da8ee28f2..f2d7070d1 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/mss_attribute_accessors.H
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/mss_attribute_accessors.H
@@ -28668,6 +28668,27 @@ fapi_try_exit:
 }
 
 ///
+/// @brief ATTR_START_CBS_FIFO_RESET_SKIP getter
+/// @param[out] uint8_t& reference to store the value
+/// @note Generated by gen_accessors.pl generateParameters (SYSTEM)
+/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
+/// @note  Allow skipping fifo reset during p9_start_cbs, to enable systems without cfam
+/// access to fifo registers
+/// (WAFER/RBI).
+///
+inline fapi2::ReturnCode start_cbs_fifo_reset_skip(uint8_t& o_value)
+{
+
+    FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_START_CBS_FIFO_RESET_SKIP, fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>(), o_value) );
+    return fapi2::current_err;
+
+fapi_try_exit:
+    FAPI_ERR("failed accessing ATTR_START_CBS_FIFO_RESET_SKIP: 0x%lx (system target)",
+             uint64_t(fapi2::current_err));
+    return fapi2::current_err;
+}
+
+///
 /// @brief ATTR_SYSTEM_CORECACHE_SKEWADJ_DISABLE getter
 /// @param[out] uint8_t& reference to store the value
 /// @note Generated by gen_accessors.pl generateParameters (SYSTEM)
diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_start_cbs.C b/src/import/chips/p9/procedures/hwp/perv/p9_start_cbs.C
index 3ddc71375..ac3468162 100644
--- a/src/import/chips/p9/procedures/hwp/perv/p9_start_cbs.C
+++ b/src/import/chips/p9/procedures/hwp/perv/p9_start_cbs.C
@@ -69,11 +69,16 @@ fapi2::ReturnCode p9_start_cbs(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>
     fapi2::buffer<uint32_t> l_data32_cbs_cs;
     int l_timeout = 0;
     fapi2::buffer<uint8_t> l_read_attr;
+    fapi2::buffer<uint8_t> l_fifo_reset_skip;
+    const fapi2::Target<fapi2::TARGET_TYPE_SYSTEM> FAPI_SYSTEM;
     FAPI_INF("p9_start_cbs: Entering ...");
 
     FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_EC_FEATURE_HW402019_PIBRESET_DELAY,
                            i_target_chip, l_read_attr));
 
+    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_START_CBS_FIFO_RESET_SKIP,
+                           FAPI_SYSTEM, l_fifo_reset_skip));
+
     FAPI_DBG("Clearing  Selfboot message register before every boot ");
     // buffer is init value is 0
     FAPI_TRY(fapi2::putCfamRegister(i_target_chip, PERV_SB_MSG_FSI, l_data32));
@@ -163,8 +168,11 @@ fapi2::ReturnCode p9_start_cbs(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>
         fapi2::delay(P9_PIBRESET_HW_NS_DELAY, P9_PIBRESET_SIM_CYCLE_DELAY);
     }
 
-    FAPI_DBG("FIFO reset");
-    FAPI_TRY(fapi2::putCfamRegister(i_target_chip, PERV_FSB_FSB_DOWNFIFO_RESET_FSI, FIFO_RESET));
+    if ( !l_fifo_reset_skip )
+    {
+        FAPI_DBG("FIFO reset");
+        FAPI_TRY(fapi2::putCfamRegister(i_target_chip, PERV_FSB_FSB_DOWNFIFO_RESET_FSI, FIFO_RESET));
+    }
 
     if ( i_sbe_start )
     {
diff --git a/src/import/chips/p9/procedures/xml/attribute_info/pervasive_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/pervasive_attributes.xml
index 51298b4d4..d0444806d 100755
--- a/src/import/chips/p9/procedures/xml/attribute_info/pervasive_attributes.xml
+++ b/src/import/chips/p9/procedures/xml/attribute_info/pervasive_attributes.xml
@@ -744,6 +744,16 @@
 </attribute>
 
 <attribute>
+  <id>ATTR_START_CBS_FIFO_RESET_SKIP</id>
+  <targetType>TARGET_TYPE_SYSTEM</targetType>
+  <description>Allow skipping fifo reset during p9_start_cbs,
+  to enable systems without cfam access to fifo registers (WAFER/RBI). </description>
+  <valueType>uint8</valueType>
+  <enum>FALSE = 0x0,TRUE = 0x1</enum>
+  <initToZero/>
+</attribute>
+
+<attribute>
   <id>ATTR_SYSTEM_CORECACHE_SKEWADJ_DISABLE</id>
   <targetType>TARGET_TYPE_SYSTEM</targetType>
   <description>To allow for selective enablement for lab testing