Update mss_decode_shadow_regs to use library MRS decoders

Change-Id: I795c57762e2f86390a2bd9c028b62e57450be0f0
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/31777
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: JACOB L. HARVEY <jlharvey@us.ibm.com>
Reviewed-by: STEPHEN GLANCY <sglancy@us.ibm.com>
Reviewed-by: Brian R. Silver <bsilver@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/31908
Reviewed-by: Hostboot Team <hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>

10 files changed, 581 insertions, 138 deletions

diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs00.C b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs00.C
index 9f2aafc01..1fcbe1b79 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs00.C
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs00.C
@@ -186,50 +186,77 @@ fapi_try_exit:
 }
 
 ///
-/// @brief Given a CCS instruction which contains address bits with an encoded MRS0,
-/// decode and trace the contents
+/// @brief Helper function for mrs00_decode
 /// @param[in] i_inst the CCS instruction
 /// @param[in] i_rank ths rank in question
+/// @param[out] o_burst_length the burst length
+/// @param[out] o_read_burst_type the burst type
+/// @param[out] o_dll_reset the dll reset bit
+/// @param[out] o_test_mode the test mode bit
+/// @param[out] o_wr_index the write index
+/// @param[out] o_cas_latency the cas latency
 /// @return FAPI2_RC_SUCCESS iff ok
 ///
-fapi2::ReturnCode mrs00_decode(const ccs::instruction_t<TARGET_TYPE_MCBIST>& i_inst,
-                               const uint64_t i_rank)
+fapi2::ReturnCode mrs00_decode_helper(const ccs::instruction_t<TARGET_TYPE_MCBIST>& i_inst,
+                                      const uint64_t i_rank,
+                                      uint8_t& o_burst_length,
+                                      uint8_t& o_read_burst_type,
+                                      uint8_t& o_dll_reset,
+                                      uint8_t& o_test_mode,
+                                      fapi2::buffer<uint8_t>& o_wr_index,
+                                      fapi2::buffer<uint8_t>& o_cas_latency)
 {
     static const uint8_t wr_map[9] = { 10, 12, 14, 16, 18, 20, 24, 22, 26 };
 
-    uint8_t l_burst_length = 0;
-    uint8_t l_read_burst_type = 0;
-    uint8_t l_dll_reset = 0;
-    uint8_t l_test_mode = 0;
+    o_wr_index = 0;
+    o_cas_latency = 0;
 
-    fapi2::buffer<uint8_t> l_wr_index;
-    fapi2::buffer<uint8_t> l_cas_latency;
-
-    i_inst.arr0.extractToRight<A0, 2>(l_burst_length);
-    l_read_burst_type = i_inst.arr0.getBit<A3>();
-    l_test_mode = i_inst.arr0.getBit<A7>();
-    l_dll_reset = i_inst.arr0.getBit<A8>();
+    i_inst.arr0.extractToRight<A0, 2>(o_burst_length);
+    o_read_burst_type = i_inst.arr0.getBit<A3>();
+    o_test_mode = i_inst.arr0.getBit<A7>();
+    o_dll_reset = i_inst.arr0.getBit<A8>();
 
     // CAS Latency takes a little effort - the bits aren't contiguous
-    l_cas_latency.writeBit<3>(i_inst.arr0.getBit<A12>());
-    l_cas_latency.writeBit<4>(i_inst.arr0.getBit<A6>());
-    l_cas_latency.writeBit<5>(i_inst.arr0.getBit<A5>());
-    l_cas_latency.writeBit<6>(i_inst.arr0.getBit<A4>());
-    l_cas_latency.writeBit<7>(i_inst.arr0.getBit<A2>());
+    o_cas_latency.writeBit<3>(i_inst.arr0.getBit<A12>());
+    o_cas_latency.writeBit<4>(i_inst.arr0.getBit<A6>());
+    o_cas_latency.writeBit<5>(i_inst.arr0.getBit<A5>());
+    o_cas_latency.writeBit<6>(i_inst.arr0.getBit<A4>());
+    o_cas_latency.writeBit<7>(i_inst.arr0.getBit<A2>());
 
     // Write Recovery/Read to Precharge is not contiguous either.
-    l_wr_index.writeBit<4>(i_inst.arr0.getBit<A13>());
-    l_wr_index.writeBit<5>(i_inst.arr0.getBit<A11>());
-    l_wr_index.writeBit<6>(i_inst.arr0.getBit<A10>());
-    l_wr_index.writeBit<7>(i_inst.arr0.getBit<A9>());
+    o_wr_index.writeBit<4>(i_inst.arr0.getBit<A13>());
+    o_wr_index.writeBit<5>(i_inst.arr0.getBit<A11>());
+    o_wr_index.writeBit<6>(i_inst.arr0.getBit<A10>());
+    o_wr_index.writeBit<7>(i_inst.arr0.getBit<A9>());
 
     FAPI_INF("MR0 Decode BL: 0x%x, RBT: 0x%x, CL: 0x%x, TM: 0x%x, DLL_RESET: 0x%x, WR: (0x%x)0x%x",
-             l_burst_length, l_read_burst_type, uint8_t(l_cas_latency), l_test_mode, l_dll_reset,
-             wr_map[uint8_t(l_wr_index)], uint8_t(l_wr_index));
+             o_burst_length, o_read_burst_type, uint8_t(o_cas_latency), o_test_mode, o_dll_reset,
+             wr_map[uint8_t(o_wr_index)], uint8_t(o_wr_index));
 
     return FAPI2_RC_SUCCESS;
 }
 
+///
+/// @brief Given a CCS instruction which contains address bits with an encoded MRS0,
+/// decode and trace the contents
+/// @param[in] i_inst the CCS instruction
+/// @param[in] i_rank ths rank in question
+/// @return FAPI2_RC_SUCCESS iff ok
+///
+fapi2::ReturnCode mrs00_decode(const ccs::instruction_t<TARGET_TYPE_MCBIST>& i_inst,
+                               const uint64_t i_rank)
+{
+    uint8_t l_burst_length = 0;
+    uint8_t l_read_burst_type = 0;
+    uint8_t l_dll_reset = 0;
+    uint8_t l_test_mode = 0;
+    fapi2::buffer<uint8_t> l_wr_index;
+    fapi2::buffer<uint8_t> l_cas_latency;
+
+    return mrs00_decode_helper(i_inst, i_rank, l_burst_length, l_read_burst_type, l_dll_reset, l_test_mode,
+                               l_wr_index, l_cas_latency);
+}
+
 fapi2::ReturnCode (*mrs00_data::make_ccs_instruction)(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
         const mrs00_data& i_data,
         ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST>& io_inst,
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs01.C b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs01.C
index f4a25496a..99cffe51a 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs01.C
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs01.C
@@ -172,6 +172,50 @@ fapi_try_exit:
 }
 
 ///
+/// @brief Helper function for mrs01_decode
+/// @param[in] i_inst the CCS instruction
+/// @param[in] i_rank ths rank in question
+/// @param[out] o_dll_enable the dll enable bit
+/// @param[out] o_wrl_enable the write leveling enable bit
+/// @param[out] o_tdqs the tdqs enable bit
+/// @param[out] o_qoff the qoff bit
+/// @param[out] o_odic the output driver impedance control setting
+/// @param[out] o_additive_latency the additive latency setting
+/// @param[out] o_rtt_nom the rtt_nom setting
+/// @return FAPI2_RC_SUCCESS iff ok
+///
+fapi2::ReturnCode mrs01_decode_helper(const ccs::instruction_t<TARGET_TYPE_MCBIST>& i_inst,
+                                      const uint64_t i_rank,
+                                      uint8_t& o_dll_enable,
+                                      uint8_t& o_wrl_enable,
+                                      uint8_t& o_tdqs,
+                                      uint8_t& o_qoff,
+                                      fapi2::buffer<uint8_t>& o_odic,
+                                      fapi2::buffer<uint8_t>& o_additive_latency,
+                                      fapi2::buffer<uint8_t>& o_rtt_nom)
+{
+    o_odic = 0;
+    o_additive_latency = 0;
+    o_rtt_nom = 0;
+
+    o_dll_enable = i_inst.arr0.getBit<A0>();
+    o_wrl_enable = i_inst.arr0.getBit<A7>();
+    o_tdqs = i_inst.arr0.getBit<A11>();
+    o_qoff = i_inst.arr0.getBit<A12>();
+
+    mss::swizzle<6, 2, A2>(i_inst.arr0, o_odic);
+    mss::swizzle<6, 2, A4>(i_inst.arr0, o_additive_latency);
+    mss::swizzle<5, 3, A10>(i_inst.arr0, o_rtt_nom);
+
+    FAPI_INF("MR1 rank %d decode: DLL_ENABLE: 0x%x, ODIC: 0x%x, AL: 0x%x, WLE: 0x%x, "
+             "RTT_NOM: 0x%x, TDQS: 0x%x, QOFF: 0x%x", i_rank,
+             o_dll_enable, uint8_t(o_odic), uint8_t(o_additive_latency), o_wrl_enable, uint8_t(o_rtt_nom),
+             o_tdqs, o_qoff);
+
+    return FAPI2_RC_SUCCESS;
+}
+
+///
 /// @brief Given a CCS instruction which contains address bits with an encoded MRS1,
 /// decode and trace the contents
 /// @param[in] i_inst the CCS instruction
@@ -181,25 +225,16 @@ fapi_try_exit:
 fapi2::ReturnCode mrs01_decode(const ccs::instruction_t<TARGET_TYPE_MCBIST>& i_inst,
                                const uint64_t i_rank)
 {
+    uint8_t l_dll_enable = 0;
+    uint8_t l_wrl_enable = 0;
+    uint8_t l_tdqs = 0;
+    uint8_t l_qoff = 0;
     fapi2::buffer<uint8_t> l_odic;
     fapi2::buffer<uint8_t> l_additive_latency;
     fapi2::buffer<uint8_t> l_rtt_nom;
 
-    uint8_t l_dll_enable = i_inst.arr0.getBit<A0>();
-    uint8_t l_wrl_enable = i_inst.arr0.getBit<A7>();
-    uint8_t l_tdqs = i_inst.arr0.getBit<A11>();
-    uint8_t l_qoff = i_inst.arr0.getBit<A12>();
-
-    mss::swizzle<6, 2, A2>(i_inst.arr0, l_odic);
-    mss::swizzle<6, 2, A4>(i_inst.arr0, l_additive_latency);
-    mss::swizzle<5, 3, A10>(i_inst.arr0, l_rtt_nom);
-
-    FAPI_INF("MR1 rank %d decode: DLL_ENABLE: 0x%x, ODIC: 0x%x, AL: 0x%x, WLE: 0x%x, "
-             "RTT_NOM: 0x%x, TDQS: 0x%x, QOFF: 0x%x", i_rank,
-             l_dll_enable, uint8_t(l_odic), uint8_t(l_additive_latency), l_wrl_enable, uint8_t(l_rtt_nom),
-             l_tdqs, l_qoff);
-
-    return FAPI2_RC_SUCCESS;
+    return mrs01_decode_helper(i_inst, i_rank, l_dll_enable, l_wrl_enable, l_tdqs, l_qoff, l_odic,
+                               l_additive_latency, l_rtt_nom);
 }
 
 fapi2::ReturnCode (*mrs01_data::make_ccs_instruction)(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs02.C b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs02.C
index 4927bbe3b..11a2dced9 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs02.C
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs02.C
@@ -177,6 +177,38 @@ fapi_try_exit:
 }
 
 ///
+/// @brief Helper function for mrs02_decode
+/// @param[in] i_inst the CCS instruction
+/// @param[in] i_rank the rank in question
+/// @param[out] o_write_crc the write crc bit
+/// @param[out] o_lpasr the low power array self refresh setting
+/// @param[out] o_cwl the cas write latency setting
+/// @param[out] o_rtt_wr the rtt_wr setting
+/// @return FAPI2_RC_SUCCESS iff ok
+///
+fapi2::ReturnCode mrs02_decode_helper(const ccs::instruction_t<TARGET_TYPE_MCBIST>& i_inst,
+                                      const uint64_t i_rank,
+                                      uint8_t& o_write_crc,
+                                      fapi2::buffer<uint8_t>& o_lpasr,
+                                      fapi2::buffer<uint8_t>& o_cwl,
+                                      fapi2::buffer<uint8_t>& o_rtt_wr)
+{
+    o_lpasr = 0;
+    o_cwl = 0;
+    o_rtt_wr = 0;
+
+    o_write_crc = i_inst.arr0.getBit<A12>();
+    mss::swizzle<5, 3, A5>(i_inst.arr0, o_cwl);
+    mss::swizzle<6, 2, A7>(i_inst.arr0, o_lpasr);
+    mss::swizzle<5, 3, A11>(i_inst.arr0, o_rtt_wr);
+
+    FAPI_INF("MR2 rank %d deocode: LPASR: 0x%x, CWL: 0x%x, RTT_WR: 0x%x, WRITE_CRC: 0x%x", i_rank,
+             uint8_t(o_lpasr), uint8_t(o_cwl), uint8_t(o_rtt_wr), o_write_crc);
+
+    return FAPI2_RC_SUCCESS;
+}
+
+///
 /// @brief Given a CCS instruction which contains address bits with an encoded MRS2,
 /// decode and trace the contents
 /// @param[in] i_inst the CCS instruction
@@ -186,19 +218,12 @@ fapi_try_exit:
 fapi2::ReturnCode mrs02_decode(const ccs::instruction_t<TARGET_TYPE_MCBIST>& i_inst,
                                const uint64_t i_rank)
 {
+    uint8_t l_write_crc = 0;
     fapi2::buffer<uint8_t> l_lpasr;
     fapi2::buffer<uint8_t> l_cwl;
     fapi2::buffer<uint8_t> l_rtt_wr;
 
-    uint8_t l_write_crc = i_inst.arr0.getBit<A12>();
-    mss::swizzle<5, 3, A5>(i_inst.arr0, l_cwl);
-    mss::swizzle<6, 2, A7>(i_inst.arr0, l_lpasr);
-    mss::swizzle<5, 3, A11>(i_inst.arr0, l_rtt_wr);
-
-    FAPI_INF("MR2 rank %d deocode: LPASR: 0x%x, CWL: 0x%x, RTT_WR: 0x%x, WRITE_CRC: 0x%x", i_rank,
-             uint8_t(l_lpasr), uint8_t(l_cwl), uint8_t(l_rtt_wr), l_write_crc);
-
-    return FAPI2_RC_SUCCESS;
+    return mrs02_decode_helper(i_inst, i_rank, l_write_crc, l_lpasr, l_cwl, l_rtt_wr);
 }
 
 fapi2::ReturnCode (*mrs02_data::make_ccs_instruction)(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs03.C b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs03.C
index 45ba9e8dd..5f26b4317 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs03.C
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs03.C
@@ -137,8 +137,8 @@ fapi2::ReturnCode mrs03(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
 
     l_crc_wr_latency_buffer = crc_wr_latency_map[i_data.iv_crc_wr_latency - LOWEST_WL];
 
-    mss::swizzle<A0, 2, 7>(fapi2::buffer<uint8_t>(i_data.iv_mpr_mode), io_inst.arr0);
-    io_inst.arr0.writeBit<A2>(i_data.iv_mpr_page);
+    mss::swizzle<A0, 2, 7>(fapi2::buffer<uint8_t>(i_data.iv_mpr_page), io_inst.arr0);
+    io_inst.arr0.writeBit<A2>(i_data.iv_mpr_mode);
     io_inst.arr0.writeBit<A3>(i_data.iv_geardown);
     io_inst.arr0.writeBit<A4>(i_data.iv_pda);
     io_inst.arr0.writeBit<A5>(i_data.iv_temp_readout);
@@ -156,37 +156,74 @@ fapi_try_exit:
 }
 
 ///
+/// @brief Helper function for mrs03_decode
+/// @param[in] i_inst the CCS instruction
+/// @param[in] i_rank the rank in question
+/// @param[out] o_mpr_mode the mpr operation setting
+/// @param[out] o_geardown the geardown mode setting
+/// @param[out] o_pda the per dram addressability setting
+/// @param[out] o_temp_readout the temperature sensor readout setting
+/// @param[out] o_mpr_page the mpr page selection
+/// @param[out] o_fine_refresh the fine granularity refresh mode setting
+/// @param[out] o_crc_wr_latency_buffer the write cmd latency when crc and dm are enabled
+/// @param[out] o_read_fromat the mpr read format setting
+/// @return FAPI2_RC_SUCCESS iff ok
+///
+fapi2::ReturnCode mrs03_decode_helper(const ccs::instruction_t<TARGET_TYPE_MCBIST>& i_inst,
+                                      const uint64_t i_rank,
+                                      uint8_t& o_mpr_mode,
+                                      uint8_t& o_geardown,
+                                      uint8_t& o_pda,
+                                      uint8_t& o_temp_readout,
+                                      fapi2::buffer<uint8_t>& o_mpr_page,
+                                      fapi2::buffer<uint8_t>& o_fine_refresh,
+                                      fapi2::buffer<uint8_t>& o_crc_wr_latency_buffer,
+                                      fapi2::buffer<uint8_t>& o_read_format)
+{
+    o_mpr_page = 0;
+    o_fine_refresh = 0;
+    o_crc_wr_latency_buffer = 0;
+    o_read_format = 0;
+
+    o_mpr_mode = i_inst.arr0.getBit<A2>();
+    o_geardown = i_inst.arr0.getBit<A3>();
+    o_pda = i_inst.arr0.getBit<A4>();
+    o_temp_readout = i_inst.arr0.getBit<A5>();
+
+    mss::swizzle<6, 2, A1>(i_inst.arr0, o_mpr_page);
+    mss::swizzle<5, 3, A8>(i_inst.arr0, o_fine_refresh);
+    mss::swizzle<6, 2, A10>(i_inst.arr0, o_crc_wr_latency_buffer);
+    mss::swizzle<6, 2, A12>(i_inst.arr0, o_read_format);
+
+    FAPI_INF("MR3 rank %d decode: MPR_MODE: 0x%x, MPR_PAGE: 0x%x, GD: 0x%x, PDA: 0x%x, "
+             "TEMP: 0x%x FR: 0x%x, CRC_WL: 0x%x, RF: 0x%x", i_rank,
+             uint8_t(o_mpr_mode), o_mpr_page, o_geardown, o_pda, uint8_t(o_temp_readout),
+             uint8_t(o_fine_refresh), uint8_t(o_crc_wr_latency_buffer), uint8_t(o_read_format));
+
+    return FAPI2_RC_SUCCESS;
+}
+
+///
 /// @brief Given a CCS instruction which contains address bits with an encoded MRS3,
 /// decode and trace the contents
 /// @param[in] i_inst the CCS instruction
-/// @param[in] i_rank ths rank in question
-/// @return void
+/// @param[in] i_rank the rank in question
+/// @return FAPI2_RC_SUCCESS iff ok
 ///
 fapi2::ReturnCode mrs03_decode(const ccs::instruction_t<TARGET_TYPE_MCBIST>& i_inst,
                                const uint64_t i_rank)
 {
-    fapi2::buffer<uint8_t> l_mpr_mode;
-
+    uint8_t l_mpr_mode = 0;
+    uint8_t l_geardown = 0;
+    uint8_t l_pda = 0;
+    uint8_t l_temp_readout = 0;
+    fapi2::buffer<uint8_t> l_mpr_page;
     fapi2::buffer<uint8_t> l_fine_refresh;
     fapi2::buffer<uint8_t> l_crc_wr_latency_buffer;
     fapi2::buffer<uint8_t> l_read_format;
 
-    uint8_t l_mpr_page = i_inst.arr0.getBit<A2>();
-    uint8_t l_geardown = i_inst.arr0.getBit<A3>();
-    uint8_t l_pda = i_inst.arr0.getBit<A4>();
-    uint8_t l_temp_readout = i_inst.arr0.getBit<A5>();
-
-    mss::swizzle<6, 2, A1>(i_inst.arr0, l_mpr_mode);
-    mss::swizzle<5, 3, A7>(i_inst.arr0, l_fine_refresh);
-    mss::swizzle<6, 2, A10>(i_inst.arr0, l_crc_wr_latency_buffer);
-    mss::swizzle<6, 2, A12>(i_inst.arr0, l_read_format);
-
-    FAPI_INF("MR3 rank %d decode: MPR_MODE: 0x%x, MPR_PAGE: 0x%x, GD: 0x%x, PDA: 0x%x, "
-             "TEMP: 0x%x FR: 0x%x, CRC_WL: 0x%x, RF: 0x%x", i_rank,
-             uint8_t(l_mpr_mode), l_mpr_page, l_geardown, l_pda, uint8_t(l_temp_readout),
-             uint8_t(l_fine_refresh), uint8_t(l_crc_wr_latency_buffer), uint8_t(l_read_format));
-
-    return FAPI2_RC_SUCCESS;
+    return mrs03_decode_helper(i_inst, i_rank, l_mpr_mode, l_geardown, l_pda, l_temp_readout,
+                               l_mpr_page, l_fine_refresh, l_crc_wr_latency_buffer, l_read_format);
 }
 
 fapi2::ReturnCode (*mrs03_data::make_ccs_instruction)(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs04.C b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs04.C
index 4b54b457e..f2dd366c2 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs04.C
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs04.C
@@ -163,39 +163,85 @@ fapi_try_exit:
 }
 
 ///
-/// @brief Given a CCS instruction which contains address bits with an encoded MRS4,
-/// decode and trace the contents
+/// @brief Helper function for mrs04_decode
 /// @param[in] i_inst the CCS instruction
-/// @param[in] i_rank ths rank in question
-/// @return void
+/// @param[in] i_rank the rank in question
+/// @param[out] o_max_pd_mode the maximum power down mode setting
+/// @param[out] o_temp_refresh_range the temperature controlled refresh range setting
+/// @param[out] o_temp_ref_mode the temperature controlled refresh mode setting
+/// @param[out] o_vref_mon the internal vref monitor setting
+/// @param[out] o_ref_abort the self refresh abort setting
+/// @param[out] o_rd_pre_train_mode the read preamble training mode setting
+/// @param[out] o_rd_preamble the read preamble setting
+/// @param[out] o_wr_preamble the write preamble setting
+/// @param[out] o_ppr the ppr setting
+/// @param[out] o_cs_cmd_latency_buffer the cs to cmd/addr latency mode setting
+/// @return FAPI2_RC_SUCCESS iff ok
 ///
-fapi2::ReturnCode mrs04_decode(const ccs::instruction_t<TARGET_TYPE_MCBIST>& i_inst,
-                               const uint64_t i_rank)
+fapi2::ReturnCode mrs04_decode_helper(const ccs::instruction_t<TARGET_TYPE_MCBIST>& i_inst,
+                                      const uint64_t i_rank,
+                                      uint8_t& o_max_pd_mode,
+                                      uint8_t& o_temp_refresh_range,
+                                      uint8_t& o_temp_ref_mode,
+                                      uint8_t& o_vref_mon,
+                                      uint8_t& o_ref_abort,
+                                      uint8_t& o_rd_pre_train_mode,
+                                      uint8_t& o_rd_preamble,
+                                      uint8_t& o_wr_preamble,
+                                      uint8_t& o_ppr,
+                                      fapi2::buffer<uint8_t>& o_cs_cmd_latency_buffer)
 {
-    uint8_t l_max_pd_mode = i_inst.arr0.getBit<A1>();
-    uint8_t l_temp_refresh_range = i_inst.arr0.getBit<A2>();
-    uint8_t l_temp_ref_mode = i_inst.arr0.getBit<A3>();
-    uint8_t l_vref_mon = i_inst.arr0.getBit<A4>();
+    o_max_pd_mode = i_inst.arr0.getBit<A1>();
+    o_temp_refresh_range = i_inst.arr0.getBit<A2>();
+    o_temp_ref_mode = i_inst.arr0.getBit<A3>();
+    o_vref_mon = i_inst.arr0.getBit<A4>();
 
-    fapi2::buffer<uint8_t> l_cs_cmd_latency_buffer;
-    mss::swizzle<5, 3, A8>(i_inst.arr0, l_cs_cmd_latency_buffer);
+    o_cs_cmd_latency_buffer = 0;
+    mss::swizzle<5, 3, A8>(i_inst.arr0, o_cs_cmd_latency_buffer);
 
-    uint8_t l_ref_abort = i_inst.arr0.getBit<A9>();
-    uint8_t l_rd_pre_train_mode = i_inst.arr0.getBit<A10>();
-    uint8_t l_rd_preamble = i_inst.arr0.getBit<A11>();
-    uint8_t l_wr_preamble = i_inst.arr0.getBit<A12>();
-    uint8_t l_ppr = i_inst.arr0.getBit<A13>();
+    o_ref_abort = i_inst.arr0.getBit<A9>();
+    o_rd_pre_train_mode = i_inst.arr0.getBit<A10>();
+    o_rd_preamble = i_inst.arr0.getBit<A11>();
+    o_wr_preamble = i_inst.arr0.getBit<A12>();
+    o_ppr = i_inst.arr0.getBit<A13>();
 
     FAPI_INF("MR4 rank %d decode: MAX_PD: 0x%x, TEMP_REFRESH_RANGE: 0x%x, TEMP_REF_MODE: 0x%x "
              "VREF_MON: 0x%x, CSL: 0x%x, REF_ABORT: 0x%x, RD_PTM: 0x%x, RD_PRE: 0x%x, "
              "WR_PRE: 0x%x, PPR: 0x%x", i_rank,
-             l_max_pd_mode, l_temp_refresh_range, l_temp_ref_mode, l_vref_mon,
-             uint8_t(l_cs_cmd_latency_buffer), l_ref_abort,
-             l_rd_pre_train_mode, l_rd_preamble, l_wr_preamble, l_ppr);
+             o_max_pd_mode, o_temp_refresh_range, o_temp_ref_mode, o_vref_mon,
+             uint8_t(o_cs_cmd_latency_buffer), o_ref_abort,
+             o_rd_pre_train_mode, o_rd_preamble, o_wr_preamble, o_ppr);
 
     return FAPI2_RC_SUCCESS;
 }
 
+///
+/// @brief Given a CCS instruction which contains address bits with an encoded MRS4,
+/// decode and trace the contents
+/// @param[in] i_inst the CCS instruction
+/// @param[in] i_rank the rank in question
+/// @return FAPI2_RC_SUCCESS iff ok
+///
+fapi2::ReturnCode mrs04_decode(const ccs::instruction_t<TARGET_TYPE_MCBIST>& i_inst,
+                               const uint64_t i_rank)
+{
+    uint8_t l_max_pd_mode = 0;
+    uint8_t l_temp_refresh_range = 0;
+    uint8_t l_temp_ref_mode = 0;
+    uint8_t l_vref_mon = 0;
+    uint8_t l_ref_abort = 0;
+    uint8_t l_rd_pre_train_mode = 0;
+    uint8_t l_rd_preamble = 0;
+    uint8_t l_wr_preamble = 0;
+    uint8_t l_ppr = 0;
+
+    fapi2::buffer<uint8_t> l_cs_cmd_latency_buffer;
+
+    return mrs04_decode_helper(i_inst, i_rank, l_max_pd_mode, l_temp_refresh_range, l_temp_ref_mode,
+                               l_vref_mon, l_ref_abort, l_rd_pre_train_mode, l_rd_preamble,
+                               l_wr_preamble, l_ppr, l_cs_cmd_latency_buffer);
+}
+
 fapi2::ReturnCode (*mrs04_data::make_ccs_instruction)(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
         const mrs04_data& i_data,
         ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST>& io_inst,
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs05.C b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs05.C
index a6a0204f8..e71034b4e 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs05.C
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs05.C
@@ -183,39 +183,82 @@ fapi_try_exit:
 }
 
 ///
-/// @brief Given a CCS instruction which contains address bits with an encoded MRS5,
-/// decode and trace the contents
+/// @brief Helper function for mrs05_decode
 /// @param[in] i_inst the CCS instruction
-/// @param[in] i_rank ths rank in question
-/// @return void
+/// @param[in] i_rank the rank in question
+/// @param[out] o_crc_error_clear the crc error clear setting
+/// @param[out] o_ca_parity_error_status the c/a parity error status
+/// @param[out] o_odt_input_buffer the odt input buffer during power down mode setting
+/// @param[out] o_ca_parity the c/a parity persistent error setting
+/// @param[out] o_data_mask the data mask setting
+/// @param[out] o_write_dbi the write dbi setting
+/// @param[out] o_read_dbi the read dbi setting
+/// @param[out] o_ca_parity_latency_buffer the c/a parity latency mode setting
+/// @param[out] o_rtt_park_buffer the rtt_park setting
+/// @return FAPI2_RC_SUCCESS iff ok
 ///
-fapi2::ReturnCode mrs05_decode(const ccs::instruction_t<TARGET_TYPE_MCBIST>& i_inst,
-                               const uint64_t i_rank)
+fapi2::ReturnCode mrs05_decode_helper(const ccs::instruction_t<TARGET_TYPE_MCBIST>& i_inst,
+                                      const uint64_t i_rank,
+                                      uint8_t& o_crc_error_clear,
+                                      uint8_t& o_ca_parity_error_status,
+                                      uint8_t& o_odt_input_buffer,
+                                      uint8_t& o_ca_parity,
+                                      uint8_t& o_data_mask,
+                                      uint8_t& o_write_dbi,
+                                      uint8_t& o_read_dbi,
+                                      fapi2::buffer<uint8_t>& o_ca_parity_latency_buffer,
+                                      fapi2::buffer<uint8_t>& o_rtt_park_buffer)
 {
-    fapi2::buffer<uint8_t> l_ca_parity_latency_buffer;
-    fapi2::buffer<uint8_t> l_rtt_park_buffer;
+    o_ca_parity_latency_buffer = 0;
+    o_rtt_park_buffer = 0;
 
-    mss::swizzle<5, 3, A2>(i_inst.arr0, l_ca_parity_latency_buffer);
-    mss::swizzle<5, 3, A8>(i_inst.arr0, l_rtt_park_buffer);
+    mss::swizzle<5, 3, A2>(i_inst.arr0, o_ca_parity_latency_buffer);
+    mss::swizzle<5, 3, A8>(i_inst.arr0, o_rtt_park_buffer);
 
-    uint8_t l_crc_error_clear = i_inst.arr0.getBit<A3>();
-    uint8_t l_ca_parity_error_status = i_inst.arr0.getBit<A4>();
-    uint8_t l_odt_input_buffer = i_inst.arr0.getBit<A5>();
+    o_crc_error_clear = i_inst.arr0.getBit<A3>();
+    o_ca_parity_error_status = i_inst.arr0.getBit<A4>();
+    o_odt_input_buffer = i_inst.arr0.getBit<A5>();
 
-    uint8_t l_ca_parity = i_inst.arr0.getBit<A9>();
-    uint8_t l_data_mask = i_inst.arr0.getBit<A10>();
-    uint8_t l_write_dbi = i_inst.arr0.getBit<A11>();
-    uint8_t l_read_dbi = i_inst.arr0.getBit<A12>();
+    o_ca_parity = i_inst.arr0.getBit<A9>();
+    o_data_mask = i_inst.arr0.getBit<A10>();
+    o_write_dbi = i_inst.arr0.getBit<A11>();
+    o_read_dbi = i_inst.arr0.getBit<A12>();
 
     FAPI_INF("MR5 rank %d decode: CAPL: 0x%x, CRC_EC: 0x%x, CA_PES: 0x%x, ODT_IB: 0x%x "
              "RTT_PARK: 0x%x, CAP: 0x%x, DM: 0x%x, WDBI: 0x%x, RDBI: 0x%x", i_rank,
-             uint8_t(l_ca_parity_latency_buffer), l_crc_error_clear, l_ca_parity_error_status,
-             l_odt_input_buffer, uint8_t(l_rtt_park_buffer), l_ca_parity, l_data_mask,
-             l_write_dbi, l_read_dbi);
+             uint8_t(o_ca_parity_latency_buffer), o_crc_error_clear, o_ca_parity_error_status,
+             o_odt_input_buffer, uint8_t(o_rtt_park_buffer), o_ca_parity, o_data_mask,
+             o_write_dbi, o_read_dbi);
 
     return FAPI2_RC_SUCCESS;
 }
 
+///
+/// @brief Given a CCS instruction which contains address bits with an encoded MRS5,
+/// decode and trace the contents
+/// @param[in] i_inst the CCS instruction
+/// @param[in] i_rank ths rank in question
+/// @return FAPI2_RC_SUCCESS iff ok
+///
+fapi2::ReturnCode mrs05_decode(const ccs::instruction_t<TARGET_TYPE_MCBIST>& i_inst,
+                               const uint64_t i_rank)
+{
+    fapi2::buffer<uint8_t> l_ca_parity_latency_buffer;
+    fapi2::buffer<uint8_t> l_rtt_park_buffer;
+
+    uint8_t l_crc_error_clear = 0;
+    uint8_t l_ca_parity_error_status = 0;
+    uint8_t l_odt_input_buffer = 0;
+    uint8_t l_ca_parity = 0;
+    uint8_t l_data_mask = 0;
+    uint8_t l_write_dbi = 0;
+    uint8_t l_read_dbi = 0;
+
+    return mrs05_decode_helper(i_inst, i_rank, l_crc_error_clear, l_ca_parity_error_status,
+                               l_odt_input_buffer, l_ca_parity, l_data_mask, l_write_dbi,
+                               l_read_dbi, l_ca_parity_latency_buffer, l_rtt_park_buffer);
+}
+
 fapi2::ReturnCode (*mrs05_data::make_ccs_instruction)(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
         const mrs05_data& i_data,
         ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST>& io_inst,
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs06.C b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs06.C
index 301af2f7d..031a7a283 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs06.C
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs06.C
@@ -142,28 +142,54 @@ fapi_try_exit:
 }
 
 ///
+/// @brief Helper function for mrs06_decode
+/// @param[in] i_inst the CCS instruction
+/// @param[in] i_rank the rank in question
+/// @param[out] o_vrefdq_train_range the vrefdq training range setting
+/// @param[out] o_vrefdq_train_enable the vrefdq training enable setting
+/// @param[out] o_tccd_l_buffer the tccd_l setting
+/// @param[out] o_vrefdq_train_value_buffer the vrefdq training value
+/// @return FAPI2_RC_SUCCESS iff ok
+///
+fapi2::ReturnCode mrs06_decode_helper(const ccs::instruction_t<TARGET_TYPE_MCBIST>& i_inst,
+                                      const uint64_t i_rank,
+                                      uint8_t& o_vrefdq_train_range,
+                                      uint8_t& o_vrefdq_train_enable,
+                                      fapi2::buffer<uint8_t>& o_tccd_l_buffer,
+                                      fapi2::buffer<uint8_t>& o_vrefdq_train_value_buffer)
+{
+    o_tccd_l_buffer = 0;
+    o_vrefdq_train_value_buffer = 0;
+
+    mss::swizzle<2, 6, A5>(i_inst.arr0, o_vrefdq_train_value_buffer);
+    o_vrefdq_train_range = i_inst.arr0.getBit<A6>();
+    o_vrefdq_train_enable = i_inst.arr0.getBit<A7>();
+    mss::swizzle<5, 3, A12>(i_inst.arr0, o_tccd_l_buffer);
+
+    FAPI_INF("MR6 rank %d decode: TRAIN_V: 0x%x, TRAIN_R: 0x%x, TRAIN_E: 0x%x, TCCD_L: 0x%x", i_rank,
+             uint8_t(o_vrefdq_train_value_buffer), o_vrefdq_train_range,
+             o_vrefdq_train_enable, uint8_t(o_tccd_l_buffer));
+
+    return FAPI2_RC_SUCCESS;
+}
+
+///
 /// @brief Given a CCS instruction which contains address bits with an encoded MRS6,
 /// decode and trace the contents
 /// @param[in] i_inst the CCS instruction
-/// @param[in] i_rank ths rank in question
-/// @return void
+/// @param[in] i_rank the rank in question
+/// @return FAPI2_RC_SUCCESS iff ok
 ///
 fapi2::ReturnCode mrs06_decode(const ccs::instruction_t<TARGET_TYPE_MCBIST>& i_inst,
                                const uint64_t i_rank)
 {
     fapi2::buffer<uint8_t> l_tccd_l_buffer;
     fapi2::buffer<uint8_t> l_vrefdq_train_value_buffer;
+    uint8_t l_vrefdq_train_range = 0;
+    uint8_t l_vrefdq_train_enable = 0;
 
-    mss::swizzle<2, 6, A5>(i_inst.arr0, l_vrefdq_train_value_buffer);
-    uint8_t l_vrefdq_train_range = i_inst.arr0.getBit<A6>();
-    uint8_t l_vrefdq_train_enable = i_inst.arr0.getBit<A7>();
-    mss::swizzle<5, 3, A12>(i_inst.arr0, l_tccd_l_buffer);
-
-    FAPI_INF("MR6 rank %d decode: TRAIN_V: 0x%x, TRAIN_R: 0x%x, TRAIN_E: 0x%x, TCCD_L: 0x%x", i_rank,
-             uint8_t(l_vrefdq_train_value_buffer), l_vrefdq_train_range,
-             l_vrefdq_train_enable, uint8_t(l_tccd_l_buffer));
-
-    return FAPI2_RC_SUCCESS;
+    return mrs06_decode_helper(i_inst, i_rank, l_vrefdq_train_range, l_vrefdq_train_enable,
+                               l_tccd_l_buffer, l_vrefdq_train_value_buffer);
 }
 
 fapi2::ReturnCode (*mrs06_data::make_ccs_instruction)(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs_load_ddr4.H b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs_load_ddr4.H
index c06ad6c3c..219b6f81a 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs_load_ddr4.H
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs_load_ddr4.H
@@ -243,71 +243,230 @@ fapi2::ReturnCode mrs06(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
 /// @{
 
 ///
+/// @brief Helper function for mrs00_decode
+/// @param[in] i_inst the CCS instruction
+/// @param[in] i_rank the rank in question
+/// @param[out] o_burst_length the burst length
+/// @param[out] o_read_burst_type the burst type
+/// @param[out] o_dll_reset the dll reset bit
+/// @param[out] o_test_mode the test mode bit
+/// @param[out] o_wr_index the write index
+/// @param[out] o_cas_latency the cas latency
+/// @return FAPI2_RC_SUCCESS iff ok
+///
+fapi2::ReturnCode mrs00_decode_helper(const ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST>& i_inst,
+                                      const uint64_t i_rank,
+                                      uint8_t& o_burst_length,
+                                      uint8_t& o_read_burst_type,
+                                      uint8_t& o_dll_reset,
+                                      uint8_t& o_test_mode,
+                                      fapi2::buffer<uint8_t>& o_wr_index,
+                                      fapi2::buffer<uint8_t>& o_cas_latency);
+
+///
 /// @brief Given a CCS instruction which contains address bits with an encoded MRS00,
 /// decode and trace the contents
 /// @param[in] i_inst the CCS instruction
-/// @param[in] i_rank ths rank in question
-/// @return void
+/// @param[in] i_rank the rank in question
+/// @return FAPI2_RC_SUCCESS iff ok
 ///
 fapi2::ReturnCode mrs00_decode(const ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST>& i_inst,
                                const uint64_t i_rank);
 
 ///
+/// @brief Helper function for mrs01_decode
+/// @param[in] i_inst the CCS instruction
+/// @param[in] i_rank the rank in question
+/// @param[out] o_dll_enable the dll enable bit
+/// @param[out] o_wrl_enable the write leveling enable bit
+/// @param[out] o_tdqs the tdqs enable bit
+/// @param[out] o_qoff the qoff bit
+/// @param[out] o_odic the output driver impedance control setting
+/// @param[out] o_additive_latency the additive latency setting
+/// @param[out] o_rtt_nom the rtt_nom setting
+/// @return FAPI2_RC_SUCCESS iff ok
+///
+fapi2::ReturnCode mrs01_decode_helper(const ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST>& i_inst,
+                                      const uint64_t i_rank,
+                                      uint8_t& o_dll_enable,
+                                      uint8_t& o_wrl_enable,
+                                      uint8_t& o_tdqs,
+                                      uint8_t& o_qoff,
+                                      fapi2::buffer<uint8_t>& o_odic,
+                                      fapi2::buffer<uint8_t>& o_additive_latency,
+                                      fapi2::buffer<uint8_t>& o_rtt_nom);
+
+///
 /// @brief Given a CCS instruction which contains address bits with an encoded MRS01,
 /// decode and trace the contents
 /// @param[in] i_inst the CCS instruction
-/// @param[in] i_rank ths rank in question
-/// @return void
+/// @param[in] i_rank the rank in question
+/// @return FAPI2_RC_SUCCESS iff ok
 ///
 fapi2::ReturnCode mrs01_decode(const ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST>& i_inst,
                                const uint64_t i_rank);
 
 ///
+/// @brief Helper function for mrs02_decode
+/// @param[in] i_inst the CCS instruction
+/// @param[in] i_rank the rank in question
+/// @param[out] o_write_crc the write crc bit
+/// @param[out] o_lpasr the low power array self refresh setting
+/// @param[out] o_cwl the cas write latency setting
+/// @param[out] o_rtt_wr the rtt_wr setting
+/// @return FAPI2_RC_SUCCESS iff ok
+///
+fapi2::ReturnCode mrs02_decode_helper(const ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST>& i_inst,
+                                      const uint64_t i_rank,
+                                      uint8_t& o_write_crc,
+                                      fapi2::buffer<uint8_t>& o_lpasr,
+                                      fapi2::buffer<uint8_t>& o_cwl,
+                                      fapi2::buffer<uint8_t>& o_rtt_wr);
+
+///
 /// @brief Given a CCS instruction which contains address bits with an encoded MRS02,
 /// decode and trace the contents
 /// @param[in] i_inst the CCS instruction
-/// @param[in] i_rank ths rank in question
-/// @return void
+/// @param[in] i_rank the rank in question
+/// @return FAPI2_RC_SUCCESS iff ok
 ///
 fapi2::ReturnCode mrs02_decode(const ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST>& i_inst,
                                const uint64_t i_rank);
 
 ///
+/// @brief Helper function for mrs03_decode
+/// @param[in] i_inst the CCS instruction
+/// @param[in] i_rank the rank in question
+/// @param[out] o_mpr_mode the mpr operation setting
+/// @param[out] o_geardown the geardown mode setting
+/// @param[out] o_pda the per dram addressability setting
+/// @param[out] o_temp_readout the temperature sensor readout setting
+/// @param[out] o_mpr_page the mpr page selection
+/// @param[out] o_fine_refresh the fine granularity refresh mode setting
+/// @param[out] o_crc_wr_latency_buffer the write cmd latency when crc and dm are enabled
+/// @param[out] o_read_fromat the mpr read format setting
+/// @return FAPI2_RC_SUCCESS iff ok
+///
+fapi2::ReturnCode mrs03_decode_helper(const ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST>& i_inst,
+                                      const uint64_t i_rank,
+                                      uint8_t& o_mpr_mode,
+                                      uint8_t& o_geardown,
+                                      uint8_t& o_pda,
+                                      uint8_t& o_temp_readout,
+                                      fapi2::buffer<uint8_t>& o_mpr_page,
+                                      fapi2::buffer<uint8_t>& o_fine_refresh,
+                                      fapi2::buffer<uint8_t>& o_crc_wr_latency_buffer,
+                                      fapi2::buffer<uint8_t>& o_read_format);
+
+///
 /// @brief Given a CCS instruction which contains address bits with an encoded MRS03,
 /// decode and trace the contents
 /// @param[in] i_inst the CCS instruction
-/// @param[in] i_rank ths rank in question
-/// @return void
+/// @param[in] i_rank the rank in question
+/// @return FAPI2_RC_SUCCESS iff ok
 ///
 fapi2::ReturnCode mrs03_decode(const ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST>& i_inst,
                                const uint64_t i_rank);
 
 ///
+/// @brief Helper function for mrs04_decode
+/// @param[in] i_inst the CCS instruction
+/// @param[in] i_rank the rank in question
+/// @param[out] o_max_pd_mode the maximum power down mode setting
+/// @param[out] o_temp_refresh_range the temperature controlled refresh range setting
+/// @param[out] o_temp_ref_mode the temperature controlled refresh mode setting
+/// @param[out] o_vref_mon the internal vref monitor setting
+/// @param[out] o_ref_abort the self refresh abort setting
+/// @param[out] o_rd_pre_train_mode the read preamble training mode setting
+/// @param[out] o_rd_preamble the read preamble setting
+/// @param[out] o_wr_preamble the write preamble setting
+/// @param[out] o_ppr the ppr setting
+/// @param[out] o_cs_cmd_latency_buffer the cs to cmd/addr latency mode setting
+/// @return FAPI2_RC_SUCCESS iff ok
+///
+fapi2::ReturnCode mrs04_decode_helper(const ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST>& i_inst,
+                                      const uint64_t i_rank,
+                                      uint8_t& o_max_pd_mode,
+                                      uint8_t& o_temp_refresh_range,
+                                      uint8_t& o_temp_ref_mode,
+                                      uint8_t& o_vref_mon,
+                                      uint8_t& o_ref_abort,
+                                      uint8_t& o_rd_pre_train_mode,
+                                      uint8_t& o_rd_preamble,
+                                      uint8_t& o_wr_preamble,
+                                      uint8_t& o_ppr,
+                                      fapi2::buffer<uint8_t>& o_cs_cmd_latency_buffer);
+
+///
 /// @brief Given a CCS instruction which contains address bits with an encoded MRS04,
 /// decode and trace the contents
 /// @param[in] i_inst the CCS instruction
-/// @param[in] i_rank ths rank in question
-/// @return void
+/// @param[in] i_rank the rank in question
+/// @return FAPI2_RC_SUCCESS iff ok
 ///
 fapi2::ReturnCode mrs04_decode(const ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST>& i_inst,
                                const uint64_t i_rank);
 
 ///
+/// @brief Helper function for mrs05_decode
+/// @param[in] i_inst the CCS instruction
+/// @param[in] i_rank the rank in question
+/// @param[out] o_crc_error_clear the crc error clear setting
+/// @param[out] o_ca_parity_error_status the c/a parity error status
+/// @param[out] o_odt_input_buffer the odt input buffer during power down mode setting
+/// @param[out] o_ca_parity the c/a parity persistent error setting
+/// @param[out] o_data_mask the data mask setting
+/// @param[out] o_write_dbi the write dbi setting
+/// @param[out] o_read_dbi the read dbi setting
+/// @param[out] o_ca_parity_latency_buffer the c/a parity latency mode setting
+/// @param[out] o_rtt_park_buffer the rtt_park setting
+/// @return FAPI2_RC_SUCCESS iff ok
+///
+fapi2::ReturnCode mrs05_decode_helper(const ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST>& i_inst,
+                                      const uint64_t i_rank,
+                                      uint8_t& o_crc_error_clear,
+                                      uint8_t& o_ca_parity_error_status,
+                                      uint8_t& o_odt_input_buffer,
+                                      uint8_t& o_ca_parity,
+                                      uint8_t& o_data_mask,
+                                      uint8_t& o_write_dbi,
+                                      uint8_t& o_read_dbi,
+                                      fapi2::buffer<uint8_t>& o_ca_parity_latency_buffer,
+                                      fapi2::buffer<uint8_t>& o_rtt_park_buffer);
+
+///
 /// @brief Given a CCS instruction which contains address bits with an encoded MRS05,
 /// decode and trace the contents
 /// @param[in] i_inst the CCS instruction
-/// @param[in] i_rank ths rank in question
-/// @return void
+/// @param[in] i_rank the rank in question
+/// @return FAPI2_RC_SUCCESS iff ok
 ///
 fapi2::ReturnCode mrs05_decode(const ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST>& i_inst,
                                const uint64_t i_rank);
 
 ///
+/// @brief Helper function for mrs06_decode
+/// @param[in] i_inst the CCS instruction
+/// @param[in] i_rank the rank in question
+/// @param[out] o_vrefdq_train_range the vrefdq training range setting
+/// @param[out] o_vrefdq_train_enable the vrefdq training enable setting
+/// @param[out] o_tccd_l_buffer the tccd_l setting
+/// @param[out] o_vrefdq_train_value_buffer the vrefdq training value
+/// @return FAPI2_RC_SUCCESS iff ok
+///
+fapi2::ReturnCode mrs06_decode_helper(const ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST>& i_inst,
+                                      const uint64_t i_rank,
+                                      uint8_t& o_vrefdq_train_range,
+                                      uint8_t& o_vrefdq_train_enable,
+                                      fapi2::buffer<uint8_t>& o_tccd_l_buffer,
+                                      fapi2::buffer<uint8_t>& o_vrefdq_train_value_buffer);
+
+///
 /// @brief Given a CCS instruction which contains address bits with an encoded MRS06,
 /// decode and trace the contents
 /// @param[in] i_inst the CCS instruction
-/// @param[in] i_rank ths rank in question
-/// @return void
+/// @param[in] i_rank the rank in question
+/// @return FAPI2_RC_SUCCESS iff ok
 ///
 fapi2::ReturnCode mrs06_decode(const ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST>& i_inst,
                                const uint64_t i_rank);
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/phy/phy_cntrl.C b/src/import/chips/p9/procedures/hwp/memory/lib/phy/phy_cntrl.C
index bd0ff0e91..7d65ed304 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/phy/phy_cntrl.C
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/phy/phy_cntrl.C
@@ -46,6 +46,48 @@ using fapi2::TARGET_TYPE_MCA;
 namespace mss
 {
 
+// Definition of the PHY PC MR shadow registers
+// indexed by [rank_pair][MR index]
+const std::vector< std::vector<uint64_t> > pcTraits<TARGET_TYPE_MCA>::PC_MR_SHADOW_REGS =
+{
+    {
+        MCA_DDRPHY_PC_MR0_PRI_RP0_P0,
+        MCA_DDRPHY_PC_MR1_PRI_RP0_P0,
+        MCA_DDRPHY_PC_MR2_PRI_RP0_P0,
+        MCA_DDRPHY_PC_MR3_PRI_RP0_P0,
+        MCA_DDRPHY_PC_MR0_SEC_RP0_P0,
+        MCA_DDRPHY_PC_MR1_SEC_RP0_P0,
+        MCA_DDRPHY_PC_MR2_SEC_RP0_P0,
+    },
+    {
+        MCA_DDRPHY_PC_MR0_PRI_RP1_P0,
+        MCA_DDRPHY_PC_MR1_PRI_RP1_P0,
+        MCA_DDRPHY_PC_MR2_PRI_RP1_P0,
+        MCA_DDRPHY_PC_MR3_PRI_RP1_P0,
+        MCA_DDRPHY_PC_MR0_SEC_RP1_P0,
+        MCA_DDRPHY_PC_MR1_SEC_RP1_P0,
+        MCA_DDRPHY_PC_MR2_SEC_RP1_P0,
+    },
+    {
+        MCA_DDRPHY_PC_MR0_PRI_RP2_P0,
+        MCA_DDRPHY_PC_MR1_PRI_RP2_P0,
+        MCA_DDRPHY_PC_MR2_PRI_RP2_P0,
+        MCA_DDRPHY_PC_MR3_PRI_RP2_P0,
+        MCA_DDRPHY_PC_MR0_SEC_RP2_P0,
+        MCA_DDRPHY_PC_MR1_SEC_RP2_P0,
+        MCA_DDRPHY_PC_MR2_SEC_RP2_P0,
+    },
+    {
+        MCA_DDRPHY_PC_MR0_PRI_RP3_P0,
+        MCA_DDRPHY_PC_MR1_PRI_RP3_P0,
+        MCA_DDRPHY_PC_MR2_PRI_RP3_P0,
+        MCA_DDRPHY_PC_MR3_PRI_RP3_P0,
+        MCA_DDRPHY_PC_MR0_SEC_RP3_P0,
+        MCA_DDRPHY_PC_MR1_SEC_RP3_P0,
+        MCA_DDRPHY_PC_MR2_SEC_RP3_P0,
+    },
+};
+
 namespace pc
 {
 
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/phy/phy_cntrl.H b/src/import/chips/p9/procedures/hwp/memory/lib/phy/phy_cntrl.H
index 2d24dac81..9473020fa 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/phy/phy_cntrl.H
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/phy/phy_cntrl.H
@@ -82,6 +82,9 @@ class pcTraits<fapi2::TARGET_TYPE_MCA>
         static const uint64_t PC_CONFIG0_REG = MCA_DDRPHY_PC_CONFIG0_P0;
         static const uint64_t PC_CONFIG1_REG = MCA_DDRPHY_PC_CONFIG1_P0;
 
+        // MCA phy MR shadow registers, indexed by [rank_pair][MR index]
+        static const std::vector< std::vector<uint64_t> > PC_MR_SHADOW_REGS;
+
         enum
         {
             INIT_CAL_ERROR_WR_LEVEL = MCA_DDRPHY_PC_INIT_CAL_ERROR_P0_WR_LEVEL,