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| author | Chris Steffen <cwsteffen@us.ibm.com> | 2019-01-28 13:36:51 -0500 |
|---|---|---|
| committer | Daniel M. Crowell <dcrowell@us.ibm.com> | 2019-02-05 15:32:33 -0600 |
| commit | de881124f74c2a869e633fafa9a574ef8ea45ce8 (patch) | |
| tree | ad1098ab05bdf0bfc71fc42417d3a1d57034071a /src/import/chips/p9/procedures/xml/attribute_info | |
| parent | 9f1d0e3a21a1fc272bd5b418ceb2944ba93388cc (diff) | |
| download | talos-hostboot-de881124f74c2a869e633fafa9a574ef8ea45ce8.tar.gz talos-hostboot-de881124f74c2a869e633fafa9a574ef8ea45ce8.zip | |
P9 Obus MNFG CRC and ECC Error Threshold
- When in MNFG Threshold Mode, we will mask CRC/ECC Errors and
setup performance counters to tally the number of errors.
Change-Id: I16ea4af0917a7f707ef09a54a0d329bf69212365
CQ: SW455443
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/71016
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Dean Sanner <dsanner@us.ibm.com>
Reviewed-by: Megan P. Nguyen <pmegan@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/71119
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Diffstat (limited to 'src/import/chips/p9/procedures/xml/attribute_info')
| -rw-r--r-- | src/import/chips/p9/procedures/xml/attribute_info/p9_io_obus_attributes.xml | 21 |
1 files changed, 19 insertions, 2 deletions
diff --git a/src/import/chips/p9/procedures/xml/attribute_info/p9_io_obus_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/p9_io_obus_attributes.xml index 4755ba0ed..fc9efabf5 100644 --- a/src/import/chips/p9/procedures/xml/attribute_info/p9_io_obus_attributes.xml +++ b/src/import/chips/p9/procedures/xml/attribute_info/p9_io_obus_attributes.xml @@ -5,7 +5,7 @@ <!-- --> <!-- OpenPOWER HostBoot Project --> <!-- --> -<!-- Contributors Listed Below - COPYRIGHT 2015,2018 --> +<!-- Contributors Listed Below - COPYRIGHT 2015,2019 --> <!-- [+] International Business Machines Corp. --> <!-- --> <!-- --> @@ -244,7 +244,7 @@ <attribute> <id>ATTR_IO_O_MFG_STRESS_PR_OFFSET_ODD</id> <targetType>TARGET_TYPE_PROC_CHIP</targetType> - <description>i + <description> This attribute provides an a way to stress the SMP Abus Odd Lanes in Manufacturing. By applying a phase rotator offset we can further stress the phy. This is a 6-bit 2's complement value that would be @@ -255,4 +255,21 @@ <platInit/> </attribute> <!-- ********************************************************************** --> +<attribute> + <id>ATTR_IO_O_MNFG_ERROR_THRESHOLD</id> + <targetType>TARGET_TYPE_SYSTEM</targetType> + <description> + When in MNFG mode, we want to change the CRC/ECC thresholds and FIR + masks. This is put into place for our longer manufacturing test runs. + </description> + <valueType>uint8</valueType> + <enum> + NONE = 0x0, + CORNER_MODE = 0x1, + RELIABILITY_MODE = 0x2 + </enum> + <initToZero/> + <platInit/> +</attribute> +<!-- ********************************************************************** --> </attributes> |
