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author | Andre Marin <aamarin@us.ibm.com> | 2016-04-17 10:25:38 -0500 |
---|---|---|
committer | Daniel M. Crowell <dcrowell@us.ibm.com> | 2016-05-19 16:29:21 -0400 |
commit | fb65fd861d2256f9f7c2a156de63a93f49826944 (patch) | |
tree | 99214dfc6e77c024f6ff22bb42b502edd555d134 /src/import/chips/p9/procedures/xml/attribute_info/memory_mrw_attributes.xml | |
parent | 7aef891ed820618d49373e863caecbcbef30fcdd (diff) | |
download | talos-hostboot-fb65fd861d2256f9f7c2a156de63a93f49826944.tar.gz talos-hostboot-fb65fd861d2256f9f7c2a156de63a93f49826944.zip |
Add eff_config functionality needed for RIT, fix cas_latency bug & attr files
Change-Id: I508ea4b156ff26ff7c652e28510a535b90030434
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/23796
Reviewed-by: STEPHEN GLANCY <sglancy@us.ibm.com>
Tested-by: Jenkins Server
Reviewed-by: Brian R. Silver <bsilver@us.ibm.com>
Tested-by: Hostboot CI
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/23799
Tested-by: FSP CI Jenkins
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Diffstat (limited to 'src/import/chips/p9/procedures/xml/attribute_info/memory_mrw_attributes.xml')
-rwxr-xr-x | src/import/chips/p9/procedures/xml/attribute_info/memory_mrw_attributes.xml | 60 |
1 files changed, 37 insertions, 23 deletions
diff --git a/src/import/chips/p9/procedures/xml/attribute_info/memory_mrw_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/memory_mrw_attributes.xml index 80f7b7ccf..2b406a4ac 100755 --- a/src/import/chips/p9/procedures/xml/attribute_info/memory_mrw_attributes.xml +++ b/src/import/chips/p9/procedures/xml/attribute_info/memory_mrw_attributes.xml @@ -27,8 +27,6 @@ </description> <valueType>uint32</valueType> <platInit/> - <odmVisable/> - <persistRuntime/> <mssAccessorName>mrw_safemode_mem_throttled_n_commands_per_port</mssAccessorName> </attribute> @@ -40,8 +38,6 @@ </description> <valueType>uint32</valueType> <platInit/> - <odmVisable/> - <persistRuntime/> <mssAccessorName>mrw_safemode_mem_throttled_n_commands_per_slot</mssAccessorName> </attribute> @@ -51,7 +47,6 @@ <description>Machine Readable Workbook Thermal Memory Power Limit</description> <valueType>uint32</valueType> <platInit/> - <odmVisable/> <mssAccessorName>mrw_thermal_memory_power_limit</mssAccessorName> </attribute> @@ -64,8 +59,6 @@ </description> <valueType>uint8</valueType> <platInit/> - <odmVisable/> - <persistRuntime/> <mssAccessorName>mrw_dimm_power_curve_percent_uplift</mssAccessorName> </attribute> @@ -78,8 +71,6 @@ </description> <valueType>uint8</valueType> <platInit/> - <odmVisable/> - <persistRuntime/> <mssAccessorName>mrw_dimm_power_curve_percent_uplift_idle</mssAccessorName> </attribute> @@ -93,8 +84,6 @@ </description> <valueType>uint32</valueType> <platInit/> - <odmVisable/> - <persistRuntime/> <mssAccessorName>mrw_mem_m_dram_clocks</mssAccessorName> </attribute> @@ -107,8 +96,6 @@ </description> <valueType>uint32</valueType> <platInit/> - <odmVisable/> - <persistRuntime/> <mssAccessorName>mrw_max_dram_databus_util</mssAccessorName> </attribute> @@ -124,9 +111,6 @@ </description> <valueType>uint8</valueType> <platInit/> - <writeable/> - <odmVisable/> - <odmChangeable/> <mssAccessorName>mrw_mcs_prefetch_retry_threshold</mssAccessorName> </attribute> @@ -137,7 +121,6 @@ <valueType>uint8</valueType> <enum>OFF = 0x00, SLOWEXIT = 0x01, FASTEXIT = 0x02</enum> <platInit/> - <odmVisable/> <mssAccessorName>mrw_power_control_requested</mssAccessorName> </attribute> @@ -151,7 +134,6 @@ <valueType>uint8</valueType> <enum>FALSE = 0, TRUE = 1</enum> <platInit/> - <odmVisable/> <mssAccessorName>mrw_vmem_regulator_power_limit_per_dimm_adj_enable</mssAccessorName> </attribute> @@ -164,7 +146,6 @@ </description> <valueType>uint8</valueType> <platInit/> - <odmVisable/> <mssAccessorName>mrw_max_number_dimms_possible_per_vmem_regulator</mssAccessorName> </attribute> @@ -239,9 +220,8 @@ <mssAccessorName>mrw_fine_refresh_mode</mssAccessorName> </attribute> - <attribute> - <id>ATTR_MRW_TEMP_REF_RANGE</id> + <id>ATTR_MRW_TEMP_REFRESH_RANGE</id> <targetType>TARGET_TYPE_SYSTEM</targetType> <description> Temp ref range. @@ -250,8 +230,42 @@ </description> <valueType>uint8</valueType> <enum>NORMAL = 0, EXTEND = 1</enum> - <writeable/> - <mssAccessorName>mrw_temp_ref_range</mssAccessorName> + <platInit/> + <mssAccessorName>mrw_temp_refresh_range</mssAccessorName> + </attribute> + + <attribute> + <id>ATTR_MRW_DRAMINIT_RESET_DISABLE</id> + <targetType>TARGET_TYPE_SYSTEM</targetType> + <description>A disable switch for resetting the phy delay values at the beginning of calling mss_draminit_training.</description> + <valueType>uint8</valueType> + <enum>DISABLE = 1, ENABLE = 0</enum> + <platInit/> + <mssAccessorName>mrw_draminit_reset_disable</mssAccessorName> + </attribute> + + <attribute> + <id>ATTR_MRW_PREFETCH_ENABLE</id> + <targetType>TARGET_TYPE_SYSTEM</targetType> + <description>Value of on or off. Determines if prefetching enabled or not. See chapter 7 of the Centaur Workbook.</description> + <valueType>uint8</valueType> + <enum>OFF = 0, ON = 1</enum> + <platInit/> + <mssAccessorName>mrw_prefetch_enable</mssAccessorName> + </attribute> + + <attribute> + <id>ATTR_MRW_CLEANER_ENABLE</id> + <targetType>TARGET_TYPE_SYSTEM</targetType> + <description> + Value of on or off. + Determines if the cleaner of the L4 cache (write modified entries to memory on idle cycles) + enabled or not. See chapter 7 of the Centaur Workbook. + </description> + <valueType>uint8</valueType> + <enum>OFF = 0, ON = 1</enum> + <platInit/> + <mssAccessorName>mrw_cleaner_enable</mssAccessorName> </attribute> </attributes> |