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authorPrem Shanker Jha <premjha2@in.ibm.com>2016-12-14 22:50:19 -0600
committerDaniel M. Crowell <dcrowell@us.ibm.com>2017-02-02 11:01:17 -0500
commita6a1c07a1d586c037a377bea24a8e6fc287e2a96 (patch)
tree4d4acd94e5c5a310e52bd67e913df730cb30f1a7 /src/import/chips/p9/procedures/utils
parent16ed14ff481e77b04ba1b12be25f1e12f67d4176 (diff)
downloadtalos-hostboot-a6a1c07a1d586c037a377bea24a8e6fc287e2a96.tar.gz
talos-hostboot-a6a1c07a1d586c037a377bea24a8e6fc287e2a96.zip
PM: Change in self sestore region for lab.
To support a lab scenario, first instruction of a thread SPR restore region and SCOM Restore region should be a BLR instruction instead of an ATTN instruction. This prevents a thread from hitting attention if SPR restore entries don't exist for it. Change-Id: I86a268d2c8ec0ed4955dc37f338fca8f7410305e Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/33877 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Reviewed-by: ASHISH A. MORE <ashish.more@in.ibm.com> Reviewed-by: RANGANATHPRASAD G. BRAHMASAMUDRA <prasadbgr@in.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Gregory S. Still <stillgs@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/33880 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Diffstat (limited to 'src/import/chips/p9/procedures/utils')
-rwxr-xr-xsrc/import/chips/p9/procedures/utils/stopreg/p9_stop_api.C10
-rwxr-xr-xsrc/import/chips/p9/procedures/utils/stopreg/p9_stop_data_struct.H5
2 files changed, 8 insertions, 7 deletions
diff --git a/src/import/chips/p9/procedures/utils/stopreg/p9_stop_api.C b/src/import/chips/p9/procedures/utils/stopreg/p9_stop_api.C
index 66fd00afc..2842ece06 100755
--- a/src/import/chips/p9/procedures/utils/stopreg/p9_stop_api.C
+++ b/src/import/chips/p9/procedures/utils/stopreg/p9_stop_api.C
@@ -5,7 +5,7 @@
/* */
/* OpenPOWER HostBoot Project */
/* */
-/* Contributors Listed Below - COPYRIGHT 2015,2016 */
+/* Contributors Listed Below - COPYRIGHT 2015,2017 */
/* [+] International Business Machines Corp. */
/* */
/* */
@@ -526,7 +526,8 @@ StopReturnCode_t p9_stop_save_cpureg( void* const i_pImage,
&(chipHomer->coreThreadRestore[coreId][threadId].coreArea[0]);
}
- if( SWIZZLE_4_BYTE(ATTN_OPCODE) == *(uint32_t*)pThreadLocation )
+ if( ( SWIZZLE_4_BYTE(BLR_INST) == *(uint32_t*)pThreadLocation ) ||
+ ( SWIZZLE_4_BYTE(ATTN_OPCODE) == *(uint32_t*) pThreadLocation ) )
{
// table for given core id doesn't exit. It needs to be
// defined.
@@ -864,6 +865,7 @@ StopReturnCode_t p9_stop_save_scom( void* const i_pImage,
uint32_t swizzleAttn = SWIZZLE_4_BYTE(ATTN_OPCODE);
uint32_t swizzleEntry = SWIZZLE_4_BYTE(SCOM_ENTRY_START);
uint32_t index = 0;
+ uint32_t swizzleBlr = SWIZZLE_4_BYTE(BLR_INST);
for( index = 0; index < entryLimit; ++index )
{
@@ -876,8 +878,8 @@ StopReturnCode_t p9_stop_save_scom( void* const i_pImage,
}
if( (( nopInst == entrySwzAddress ) ||
- ( swizzleAttn == entrySwzAddress )) &&
- ( !pNopLocation ) )
+ ( swizzleAttn == entrySwzAddress ) ||
+ ( swizzleBlr == entrySwzAddress )) && ( !pNopLocation ) )
{
pNopLocation = &pScomEntry[index];
}
diff --git a/src/import/chips/p9/procedures/utils/stopreg/p9_stop_data_struct.H b/src/import/chips/p9/procedures/utils/stopreg/p9_stop_data_struct.H
index 08a974ae7..e9cfa29a7 100755
--- a/src/import/chips/p9/procedures/utils/stopreg/p9_stop_data_struct.H
+++ b/src/import/chips/p9/procedures/utils/stopreg/p9_stop_data_struct.H
@@ -5,7 +5,7 @@
/* */
/* OpenPOWER HostBoot Project */
/* */
-/* Contributors Listed Below - COPYRIGHT 2015,2016 */
+/* Contributors Listed Below - COPYRIGHT 2015,2017 */
/* [+] International Business Machines Corp. */
/* */
/* */
@@ -64,8 +64,7 @@ typedef struct
*/
typedef struct
{
- uint8_t threadArea[THREAD_SECTN_SIZE];
- uint8_t reserve[THREAD_AREA_SIZE - THREAD_SECTN_SIZE];
+ uint8_t threadArea[THREAD_AREA_SIZE];
uint8_t coreArea[CORE_SPR_SECTN_SIZE];
} SprRestoreArea_t;
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