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author | Prem Shanker Jha <premjha2@in.ibm.com> | 2017-04-19 06:50:30 -0500 |
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committer | Daniel M. Crowell <dcrowell@us.ibm.com> | 2017-04-22 17:17:26 -0400 |
commit | 07b17871136a124cb3c296af0a2189368711617b (patch) | |
tree | 3488de4768f4cd58758dfcd67787eda0c34dcede /src/import/chips/p9/procedures/utils | |
parent | ee309b91f8f54e0171154fa79b579d735453edac (diff) | |
download | talos-hostboot-07b17871136a124cb3c296af0a2189368711617b.tar.gz talos-hostboot-07b17871136a124cb3c296af0a2189368711617b.zip |
PM: PM: Added support for self-restore in case of LE Hypervisor - stage 3
Change-Id: Ifd5c21b88e9494aea689c291136b90bde804882e
HW-Image-Prereq: 2e8b318cb00d6a4d1c425f87d5c7f1d0fa000162
RTC: 172449
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/39420
Reviewed-by: Michael S. Floyd <mfloyd@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: AMIT KUMAR <akumar3@us.ibm.com>
Reviewed-by: Gregory S. Still <stillgs@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/39423
Reviewed-by: Hostboot Team <hostboot@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Diffstat (limited to 'src/import/chips/p9/procedures/utils')
-rwxr-xr-x | src/import/chips/p9/procedures/utils/stopreg/p9_cpu_reg_restore_instruction.H | 5 | ||||
-rwxr-xr-x | src/import/chips/p9/procedures/utils/stopreg/p9_stop_api.C | 17 |
2 files changed, 11 insertions, 11 deletions
diff --git a/src/import/chips/p9/procedures/utils/stopreg/p9_cpu_reg_restore_instruction.H b/src/import/chips/p9/procedures/utils/stopreg/p9_cpu_reg_restore_instruction.H index 650c2fd09..e5689ae82 100755 --- a/src/import/chips/p9/procedures/utils/stopreg/p9_cpu_reg_restore_instruction.H +++ b/src/import/chips/p9/procedures/utils/stopreg/p9_cpu_reg_restore_instruction.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* Contributors Listed Below - COPYRIGHT 2015,2017 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -60,7 +60,8 @@ enum RLDICR_CONST = 1, MTSPR_CONST1 = 467, MTMSRD_CONST1 = 178, - MR_INT = 0x7c0a0378, + MR_R0_TO_R10 = 0x7c0a0378, //mr r10, r0 + MR_R0_TO_R21 = 0x7c150378, //mr r21, r0 BLR_INST = 0x4e800020, MTSPR_BASE_OPCODE = 0x7c0003a6, ATTN_OPCODE = 0x00000200, diff --git a/src/import/chips/p9/procedures/utils/stopreg/p9_stop_api.C b/src/import/chips/p9/procedures/utils/stopreg/p9_stop_api.C index 877092097..1d34ca490 100755 --- a/src/import/chips/p9/procedures/utils/stopreg/p9_stop_api.C +++ b/src/import/chips/p9/procedures/utils/stopreg/p9_stop_api.C @@ -398,12 +398,6 @@ StopReturnCode_t updateSprEntryInImage( uint32_t* i_pSprEntryLocation, newEntry = false; } - if( P9_STOP_SPR_MSR == i_regId ) - { - regRs = 21; //use r21 for instruction generation - regRa = 21; - } - //Add SPR search instruction i.e. "ori r0, r0, SPRID" *i_pSprEntryLocation = tempInst; i_pSprEntryLocation += SIZE_PER_SPR_RESTORE_INST; @@ -445,14 +439,19 @@ StopReturnCode_t updateSprEntryInImage( uint32_t* i_pSprEntryLocation, if( P9_STOP_SPR_MSR == i_regId ) { - // Case MSR, move contents of R0 to an MSR - tempInst = getMtmsrdInstruction( regRa ); + //MSR cannot be restored completely with mtmsrd instruction. + //as it does not update ME, LE and HV bits. In self restore code + //inorder to restore MSR, contents of R21 is moved to SRR1. It also + //executes an RFID which causes contents of SRR1 to be copied to + //MSR. This allows copy of LE bit which are specifically interested + //in. Instruction below moves contents of MSR Value (in R0 ) to R21. + tempInst = SWIZZLE_4_BYTE( MR_R0_TO_R21 ); } else if (P9_STOP_SPR_HRMOR == i_regId ) { //Case HRMOR, move contents of R0 to a placeholder GPR (R10) //Thread Launcher expects HRMOR value in R10 - tempInst = SWIZZLE_4_BYTE(MR_INT); + tempInst = SWIZZLE_4_BYTE( MR_R0_TO_R10 ); } else { |