diff options
author | Prem Shanker Jha <premjha2@in.ibm.com> | 2016-09-13 04:39:47 -0500 |
---|---|---|
committer | Daniel M. Crowell <dcrowell@us.ibm.com> | 2016-10-13 10:53:04 -0400 |
commit | 0fba7aef9059abb0e650bc9dc18ae7e66ef30261 (patch) | |
tree | 01cf37dfd6843de09aee0c415ef43b90fbec1a16 /src/import/chips/p9/procedures/utils/stopreg | |
parent | 498b30de18b3157bf48697f191e70096f66e9d5e (diff) | |
download | talos-hostboot-0fba7aef9059abb0e650bc9dc18ae7e66ef30261.tar.gz talos-hostboot-0fba7aef9059abb0e650bc9dc18ae7e66ef30261.zip |
PM:Added an EQ sub-section for restoration of SCOM registers of scope quad.
Dropped a section meant for restoration of NC SCOMS. Introduced
a new EQ section. It is intended for restoring SCOM registers which
are spread across the quad.
Change-Id: Icdc5ba4affd74b454e22b576ee0866be3ace1183
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/29557
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Gregory S. Still <stillgs@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/29558
Reviewed-by: Hostboot Team <hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Diffstat (limited to 'src/import/chips/p9/procedures/utils/stopreg')
4 files changed, 15 insertions, 16 deletions
diff --git a/src/import/chips/p9/procedures/utils/stopreg/p9_stop_api.C b/src/import/chips/p9/procedures/utils/stopreg/p9_stop_api.C index 4445b520e..1e000e921 100755 --- a/src/import/chips/p9/procedures/utils/stopreg/p9_stop_api.C +++ b/src/import/chips/p9/procedures/utils/stopreg/p9_stop_api.C @@ -725,7 +725,7 @@ StopReturnCode_t editScomEntry( uint32_t i_scomAddr, uint64_t i_scomData, * @return STOP_SAVE_SUCCESS if new entry is added, STOP_SAVE_FAIL otherwise. * @note adds an entry at a given location. It can be used to add entry in * place of NOP, at the end of table or as first entry of the cache - * sub-section(L2, L3 or NC ). + * sub-section(L2, L3 or EQ ). */ StopReturnCode_t updateScomEntry( uint32_t i_scomAddr, uint64_t i_scomData, ScomEntry_t* i_scomEntry ) @@ -794,7 +794,7 @@ StopReturnCode_t p9_stop_save_scom( void* const i_pImage, { // chiplet is a cache. let us find start address of cache section // associated with given chiplet. A cache section associated with - // given chiplet is split in to L2, L3 and NC area. + // given chiplet is split in to L2, L3 and EQ area. pStopCacheScomStart = CACHE_SECTN_START(i_pImage, chipletId); } @@ -810,9 +810,9 @@ StopReturnCode_t p9_stop_save_scom( void* const i_pImage, switch( i_section ) { - case P9_STOP_SECTION_NC: + case P9_STOP_SECTION_EQ_SCOM: pScomEntry = pStopCacheScomStart->nonCacheArea; - entryLimit = MAX_NC_SCOM_ENTRIES; + entryLimit = MAX_EQ_SCOM_ENTRIES; break; case P9_STOP_SECTION_L2: diff --git a/src/import/chips/p9/procedures/utils/stopreg/p9_stop_api.H b/src/import/chips/p9/procedures/utils/stopreg/p9_stop_api.H index dcec90bfd..3901ae81a 100755 --- a/src/import/chips/p9/procedures/utils/stopreg/p9_stop_api.H +++ b/src/import/chips/p9/procedures/utils/stopreg/p9_stop_api.H @@ -103,13 +103,12 @@ typedef enum */ typedef enum { - P9_STOP_SECTION_MIN = 0, - P9_STOP_SECTION_CORE_SCOM = 1, - P9_STOP_SECTION_EQ_SCOM = 2, - P9_STOP_SECTION_NC = 2, //deprecated - P9_STOP_SECTION_L2 = 3, - P9_STOP_SECTION_L3 = 4, - P9_STOP_SECTION_MAX = 5 + P9_STOP_SECTION_MIN = 0, + P9_STOP_SECTION_CORE_SCOM = 1, + P9_STOP_SECTION_EQ_SCOM = 2, + P9_STOP_SECTION_L2 = 3, + P9_STOP_SECTION_L3 = 4, + P9_STOP_SECTION_MAX = 5 } ScomSection_t; #ifdef __cplusplus diff --git a/src/import/chips/p9/procedures/utils/stopreg/p9_stop_data_struct.H b/src/import/chips/p9/procedures/utils/stopreg/p9_stop_data_struct.H index 3de5cda27..08a974ae7 100755 --- a/src/import/chips/p9/procedures/utils/stopreg/p9_stop_data_struct.H +++ b/src/import/chips/p9/procedures/utils/stopreg/p9_stop_data_struct.H @@ -92,7 +92,7 @@ typedef struct */ typedef struct { - ScomEntry_t nonCacheArea[MAX_NC_SCOM_ENTRIES]; + ScomEntry_t nonCacheArea[MAX_EQ_SCOM_ENTRIES]; ScomEntry_t l2CacheArea[MAX_L2_SCOM_ENTRIES]; ScomEntry_t l3CacheArea[MAX_L3_SCOM_ENTRIES]; } StopCacheSection_t; diff --git a/src/import/chips/p9/procedures/utils/stopreg/p9_stop_section_defines.H b/src/import/chips/p9/procedures/utils/stopreg/p9_stop_section_defines.H index 1a8a007e8..ed34d7544 100755 --- a/src/import/chips/p9/procedures/utils/stopreg/p9_stop_section_defines.H +++ b/src/import/chips/p9/procedures/utils/stopreg/p9_stop_section_defines.H @@ -48,13 +48,13 @@ enum ONE_MB = ONE_KB * ONE_KB, TWO_MB = 2 * ONE_MB, MAX_CORE_SCOM_ENTRIES = 15, - MAX_NC_SCOM_ENTRIES = 15, + MAX_EQ_SCOM_ENTRIES = 15, MAX_L2_SCOM_ENTRIES = 16, MAX_L3_SCOM_ENTRIES = 16, MAX_CORE_ID_SUPPORTED = 23, MAX_THREAD_ID_SUPPORTED = 3, MAX_CACHE_SECTN_SIZE_PER_CHIPLET = - MAX_NC_SCOM_ENTRIES + MAX_L2_SCOM_ENTRIES + MAX_L3_SCOM_ENTRIES, + MAX_EQ_SCOM_ENTRIES + MAX_L2_SCOM_ENTRIES + MAX_L3_SCOM_ENTRIES, // start offset for SPR register restore, core scom or cache scom register // restore regions in homer image. @@ -86,14 +86,14 @@ enum CORE_SPR_SECTN_SIZE = ONE_KB, L2_AREA = (SCOM_ENTRY_SIZE * MAX_L2_SCOM_ENTRIES), L3_AREA = (SCOM_ENTRY_SIZE * MAX_L2_SCOM_ENTRIES ), - NON_CACHE_AREA = SCOM_ENTRY_SIZE * MAX_NC_SCOM_ENTRIES, + EQ_AREA = SCOM_ENTRY_SIZE * MAX_EQ_SCOM_ENTRIES, MAX_SIZE_PER_CORE = 8 * ONE_KB, SPR_RESTORE_PER_CHIP = ( MAX_SIZE_PER_CORE * ( MAX_CORE_ID_SUPPORTED + 1)) + ( INTERRUPT_HANDLER_SIZE + THREAD_LAUNCHER_SIZE), SCOM_SIZE_PER_CORE = ( MAX_CORE_SCOM_ENTRIES + 1 ) * SCOM_ENTRY_SIZE, SCOM_SIZE_PER_CHIP = SCOM_SIZE_PER_CORE * ( MAX_CORE_ID_SUPPORTED + 1), - SCOM_SIZE_PER_CACHE_CHIPLET = L2_AREA + L3_AREA + NON_CACHE_AREA + SCOM_SIZE_PER_CACHE_CHIPLET = L2_AREA + L3_AREA + EQ_AREA + SCOM_ENTRY_SIZE, //size in byte ends }; |