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author | Prem Shanker Jha <premjha2@in.ibm.com> | 2015-11-12 03:36:55 -0600 |
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committer | Stephen Cprek <smcprek@us.ibm.com> | 2016-02-19 17:08:23 -0600 |
commit | 548a746856d6095fd4585253893d78b74205f926 (patch) | |
tree | ac8bdce8358cc2aae8d6d329dc6df675d717b387 /src/import/chips/p9/procedures/utils/stopreg/p9_stop_section_defines.H | |
parent | 5c52f2606c25ccaa3d500323914257cd988c52d9 (diff) | |
download | talos-hostboot-548a746856d6095fd4585253893d78b74205f926.tar.gz talos-hostboot-548a746856d6095fd4585253893d78b74205f926.zip |
PM: Updated Stop API based on modified HOMER layout.
This commit updates the STOP APIs to accomodate changes made in HOMER
layout. CME region begins at an offset of 2MB wrt start of HOMER whereas
STOP GPE regions begins at 1 MB wrt start of HOMER. There are some
corrections for minor coding aesthetics issues.
Change-Id: I2914635fa7223654b89a084e17e33065b1655762
RTC: 140797
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/21985
Tested-by: Jenkins Server
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Diffstat (limited to 'src/import/chips/p9/procedures/utils/stopreg/p9_stop_section_defines.H')
-rwxr-xr-x | src/import/chips/p9/procedures/utils/stopreg/p9_stop_section_defines.H | 96 |
1 files changed, 96 insertions, 0 deletions
diff --git a/src/import/chips/p9/procedures/utils/stopreg/p9_stop_section_defines.H b/src/import/chips/p9/procedures/utils/stopreg/p9_stop_section_defines.H new file mode 100755 index 000000000..435931983 --- /dev/null +++ b/src/import/chips/p9/procedures/utils/stopreg/p9_stop_section_defines.H @@ -0,0 +1,96 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: chips/p9/procedures/utils/stopreg/p9_stop_section_defines.H $ */ +/* */ +/* IBM CONFIDENTIAL */ +/* */ +/* EKB Project */ +/* */ +/* COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* The source code for this program is not published or otherwise */ +/* divested of its trade secrets, irrespective of what has been */ +/* deposited with the U.S. Copyright Office. */ +/* */ +/* IBM_PROLOG_END_TAG */ + +/// +/// @file p9_stop_section_defines.H +/// @brief defines all constants associated with STOP image layout. +/// +// *HWP HW Owner : Greg Still <stillgs@us.ibm.com> +// *HWP FW Owner : Prem Shanker Jha <premjha2@in.ibm.com> +// *HWP Team : PM +// *HWP Level : 2 +// *HWP Consumed by : HB:HYP + +#ifndef _STOP_SECTION_DEFINES_H +#define _STOP_SECTION_DEFINES_H + +namespace stopImageSection +{ + +//basic constants +enum +{ + ONE_KB = 1024, + ONE_MB = ONE_KB * ONE_KB, + TWO_MB = 2 * ONE_MB, + MAX_CORE_SCOM_ENTRIES = 15, + MAX_NC_SCOM_ENTRIES = 15, + MAX_L2_SCOM_ENTRIES = 16, + MAX_L3_SCOM_ENTRIES = 16, + MAX_CORE_ID_SUPPORTED = 23, + MAX_THREAD_ID_SUPPORTED = 3, + MAX_CACHE_SECTN_SIZE_PER_CHIPLET = + MAX_NC_SCOM_ENTRIES + MAX_L2_SCOM_ENTRIES + MAX_L3_SCOM_ENTRIES, + + // start offset for SPR register restore, core scom or cache scom register + // restore regions in homer image. + CORE_SCOM_SECTN_START = ( TWO_MB + ( 256 * ONE_KB )), //offset from start of chip HOMER + CACHE_SCOM_SECTN_START = ( ONE_MB + ( 32 * ONE_KB )), // start of cache section + + //constants in HOMER's header area. + REGULAR_MODE = 0xAA, + FUSE_MODE = 0xBB, + HOMER_MAGIC_WORD = 0x484F4D4552312E30ll, + CACHE_CHIPLET_ID_MIN = 0x10, + CACHE_CHIPLET_ID_MAX = 0x15, + CORE_CHIPLET_ID_MIN = 0x20, + CORE_CHIPLET_ID_MAX = 0x37, + MAX_SPR_RESTORE_INST = 0x08, + SIZE_PER_SPR_RESTORE_INST = ((4 * sizeof(uint8_t)) / sizeof(uint32_t)), +}; + +// all section sizes below are in bytes +enum +{ + SCOM_ENTRY_SIZE = 16, + INTERRUPT_HANDLER_SIZE = 8 * ONE_KB, + THREAD_LAUNCHER_SIZE = 256, + THREAD_RESTORE_SECTN = 192, + THREAD_COMPLETION = 64, + THREAD_AREA_SIZE = ONE_KB, + THREAD_SECTN_SIZE = THREAD_RESTORE_SECTN + THREAD_COMPLETION, + CORE_SPR_SECTN_SIZE = ONE_KB, + L2_AREA = (SCOM_ENTRY_SIZE * MAX_L2_SCOM_ENTRIES), + L3_AREA = (SCOM_ENTRY_SIZE * MAX_L2_SCOM_ENTRIES ), + NON_CACHE_AREA = SCOM_ENTRY_SIZE * MAX_NC_SCOM_ENTRIES, + MAX_SIZE_PER_CORE = 8 * ONE_KB, + SPR_RESTORE_PER_CHIP = ( MAX_SIZE_PER_CORE * + ( MAX_CORE_ID_SUPPORTED + 1)) + + ( INTERRUPT_HANDLER_SIZE + THREAD_LAUNCHER_SIZE), + SCOM_SIZE_PER_CORE = ( MAX_CORE_SCOM_ENTRIES + 1 ) * SCOM_ENTRY_SIZE, + SCOM_SIZE_PER_CHIP = SCOM_SIZE_PER_CORE * ( MAX_CORE_ID_SUPPORTED + 1), + SCOM_SIZE_PER_CACHE_CHIPLET = L2_AREA + L3_AREA + NON_CACHE_AREA + + SCOM_ENTRY_SIZE, +//size in byte ends +}; + +}//stopImageSection ends + +#endif + |