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author | Jacob Harvey <jlharvey@us.ibm.com> | 2017-03-07 11:43:00 -0600 |
---|---|---|
committer | Christian R. Geddes <crgeddes@us.ibm.com> | 2017-03-16 10:32:58 -0400 |
commit | d33402a184c0f6ce2691eff8b862dc90af398f64 (patch) | |
tree | 7e3f42fc1aafef0ef7e41b9566571ef891df4100 /src/import/chips/p9/procedures/hwp | |
parent | 7270032beb560076eba4d4c8e1982dd04354f8a3 (diff) | |
download | talos-hostboot-d33402a184c0f6ce2691eff8b862dc90af398f64.tar.gz talos-hostboot-d33402a184c0f6ce2691eff8b862dc90af398f64.zip |
Change accesses to IS_SIM to use mss accessor
Change-Id: Ibadcd2d0ca7daa77705067e69f3aee042492636d
Original-Change-Id: Iafcaddbca510c29fb4a0289490b90b539dde2b13
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/37610
Reviewed-by: Brian R. Silver <bsilver@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: STEPHEN GLANCY <sglancy@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/38014
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>
Diffstat (limited to 'src/import/chips/p9/procedures/hwp')
-rw-r--r-- | src/import/chips/p9/procedures/hwp/memory/lib/mc/port.C | 16 | ||||
-rw-r--r-- | src/import/chips/p9/procedures/hwp/memory/lib/phy/write_cntrl.H | 16 |
2 files changed, 16 insertions, 16 deletions
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/mc/port.C b/src/import/chips/p9/procedures/hwp/memory/lib/mc/port.C index 0703fd828..4f5b2ad6b 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/mc/port.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/mc/port.C @@ -85,8 +85,8 @@ fapi2::ReturnCode enable_periodic_cal( const fapi2::Target<fapi2::TARGET_TYPE_MC FAPI_INF("Enable periodic cal"); - uint8_t is_sim = 0; - FAPI_TRY( mss::is_simulation(is_sim) ); + uint8_t l_sim = 0; + FAPI_TRY( mss::is_simulation(l_sim) ); // Even if we're in sim, do these so that we do the attribute work (even though the values aren't used.) FAPI_TRY( mss::eff_memcal_interval(i_target, l_memcal_interval) ); @@ -140,7 +140,7 @@ fapi2::ReturnCode enable_periodic_cal( const fapi2::Target<fapi2::TARGET_TYPE_MC fapi2::buffer<uint64_t> l_data; // Don't enable zcal in sim as we don't enable it in the PHY - l_data.writeBit<TT::CAL0Q_CAL_INTERVAL_TMR0_ENABLE>(is_sim ? 0 : 1); + l_data.writeBit<TT::CAL0Q_CAL_INTERVAL_TMR0_ENABLE>(l_sim ? 0 : 1); l_data.insertFromRight<TT::CAL0Q_TIME_BASE_TMR0, TT::CAL0Q_TIME_BASE_TMR0_LEN>(0b01); l_data.insertFromRight<TT::CAL0Q_INTERVAL_COUNTER_TMR0, TT::CAL0Q_INTERVAL_COUNTER_TMR0_LEN>(0b010000000); @@ -162,7 +162,7 @@ fapi2::ReturnCode enable_periodic_cal( const fapi2::Target<fapi2::TARGET_TYPE_MC FAPI_TRY( reset_zqcal_config(i_target) ); // No ZQCAL in sim - l_periodic_cal_config.writeBit<TT::PER_ENA_ZCAL>(is_sim ? 0 : 1); + l_periodic_cal_config.writeBit<TT::PER_ENA_ZCAL>(l_sim ? 0 : 1); // Write the ZQCAL timer reload register // # DPHY01_DDRPHY_PC_ZCAL_TIMER_RELOAD_VALUE_P0 0x00A 0x8000c0090301143f @@ -180,7 +180,7 @@ fapi2::ReturnCode enable_periodic_cal( const fapi2::Target<fapi2::TARGET_TYPE_MC // have the story above opened to investigate fapi2::buffer<uint64_t> l_zcal_timer_reload; l_zcal_timer_reload.insertFromRight<TT::ZCAL_TIMER_RELOAD_VALUE, TT::ZCAL_TIMER_RELOAD_VALUE_LEN>( - is_sim ? (l_zqcal_interval / TT::MAGIC_NUMBER_SIM) + 1 : (l_zqcal_interval / TT::MAGIC_NUMBER_NOT_SIM) + 1); + l_sim ? (l_zqcal_interval / TT::MAGIC_NUMBER_SIM) + 1 : (l_zqcal_interval / TT::MAGIC_NUMBER_NOT_SIM) + 1); FAPI_INF("zcal timer reload: 0x%016lx", l_zcal_timer_reload); FAPI_TRY( mss::putScom(i_target, TT::PHY_ZCAL_TIMER_RELOAD_REG, l_zcal_timer_reload) ); } @@ -251,7 +251,7 @@ fapi2::ReturnCode enable_periodic_cal( const fapi2::Target<fapi2::TARGET_TYPE_MC // scom 0x800(0,1)c0080301143f { # _P[0:1] // bits , scom_data, expr; # must be >= 2... // # 0:47 , 0x000000000000, any ;# reserved - // # 48:63 , 0x0000, (def_is_sim) ;# match dials + // # 48:63 , 0x0000, (def_l_sim) ;# match dials // 48:63 , ((ATTR_EFF_MEMCAL_INTERVAL/196605)+1), (def_FAST_SIM_PC==0) ;# FAST_SIM_PER_CNTR=0 // 48:63 , ((ATTR_EFF_MEMCAL_INTERVAL/765)+1), (def_FAST_SIM_PC==1) ;# FAST_SIM_PER_CNTR=1 // # 48:63 , 0x01D1, any ; # 464 = 114ms @ 1600MHz @@ -263,7 +263,7 @@ fapi2::ReturnCode enable_periodic_cal( const fapi2::Target<fapi2::TARGET_TYPE_MC } // If we're in sim, enable the fast-sim mode - l_periodic_cal_config.writeBit<TT::PER_FAST_SIM_CNTR>(is_sim); + l_periodic_cal_config.writeBit<TT::PER_FAST_SIM_CNTR>(l_sim); l_periodic_cal_config.writeBit<TT::PER_ENA_SYSCLK_ALIGN>( l_per_memcal_mode_options.getBit<BIT_SYSCLK_ALIGN>() ); @@ -292,7 +292,7 @@ fapi2::ReturnCode enable_periodic_cal( const fapi2::Target<fapi2::TARGET_TYPE_MC // have the story above opened to investigate fapi2::buffer<uint64_t> l_cal_timer_reload; l_cal_timer_reload.insertFromRight<TT::PC_CAL_TIMER_RELOAD_VALUE, TT::PC_CAL_TIMER_RELOAD_VALUE_LEN>( - is_sim ? (l_memcal_interval / TT::MAGIC_NUMBER_SIM) + 1 : (l_memcal_interval / TT::MAGIC_NUMBER_NOT_SIM) + 1); + l_sim ? (l_memcal_interval / TT::MAGIC_NUMBER_SIM) + 1 : (l_memcal_interval / TT::MAGIC_NUMBER_NOT_SIM) + 1); FAPI_INF("phy cal timer reload: 0x%016lx", l_cal_timer_reload); FAPI_TRY( mss::putScom(i_target, TT::PHY_CAL_TIMER_RELOAD_REG, l_cal_timer_reload ) ); } diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/phy/write_cntrl.H b/src/import/chips/p9/procedures/hwp/memory/lib/phy/write_cntrl.H index 390cb1012..e2566c111 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/phy/write_cntrl.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/phy/write_cntrl.H @@ -321,8 +321,8 @@ template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCA, typename TT = wcTraits<T inline fapi2::ReturnCode reset_config0( const fapi2::Target<T>& i_target ) { fapi2::buffer<uint64_t> l_data; - uint8_t l_is_sim = 0; - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_IS_SIMULATION, fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>(), l_is_sim) ); + uint8_t l_l_sim = 0; + FAPI_TRY( mss::is_simulation(l_l_sim) ); // This is a simplification - in sim we don't have DQS wire delays so we don't acccount for them BRS l_data.insertFromRight<TT::TWLO_TWLOE, TT::TWLO_TWLOE_LEN>(mss::twlo_twloe(i_target)); @@ -331,10 +331,10 @@ inline fapi2::ReturnCode reset_config0( const fapi2::Target<T>& i_target ) l_data.setBit<TT::WL_ONE_DQS_PULSE>(); // FW_WR_RD [same formula as RD_WR? max(tWTR+11,AL+tRTP+3), ATTR_EFF_DRAM_AL(0,1,2)] - // 57:62, 0b000000, (def_is_sim); # is this max? + // 57:62, 0b000000, (def_l_sim); # is this max? // 57:62, 0b100000, any; # dd0 = 17 clocks, now 32 from SWyatt { - const uint64_t FW_WR_RD = l_is_sim ? 0b000000 : 0b100000; + const uint64_t FW_WR_RD = l_l_sim ? 0b000000 : 0b100000; l_data.insertFromRight<TT::FW_WR_RD, TT::FW_WR_RD_LEN>(FW_WR_RD); } @@ -410,15 +410,15 @@ template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCA, typename TT = wcTraits<T inline fapi2::ReturnCode reset_config3( const fapi2::Target<T>& i_target ) { fapi2::buffer<uint64_t> l_data; - uint8_t l_is_sim = 0; - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_IS_SIMULATION, fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>(), l_is_sim) ); + uint8_t l_l_sim = 0; + FAPI_TRY( mss::is_simulation(l_l_sim) ); // MCA_DDRPHY_WC_CONFIG3_P0_MRS_CMD_DQ_ON is 0's - // 55:60, 0b000000, (def_is_sim); # MRS_CMD_DQ_OFF !! + // 55:60, 0b000000, (def_l_sim); # MRS_CMD_DQ_OFF !! // 55:60, 0b111111, any ; # MRS_CMD_DQ_OFF !! { - const uint64_t CMD_DQ_OFF = l_is_sim ? 0b000000 : 0b111111; + const uint64_t CMD_DQ_OFF = l_l_sim ? 0b000000 : 0b111111; l_data.insertFromRight<TT::MRS_CMD_DQ_OFF, TT::MRS_CMD_DQ_OFF_LEN>(CMD_DQ_OFF); } |