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authorBrian Silver <bsilver@us.ibm.com>2016-08-11 08:46:11 -0500
committerWilliam G. Hoffa <wghoffa@us.ibm.com>2016-08-17 14:34:36 -0400
commit644984fb1230696d7990d32b22fd551d9090a862 (patch)
treec72c57481ea173a07e2fb7e3c598eefcd453f503 /src/import/chips/p9/procedures/hwp
parent012957d5c617eea86a2be35337956a535b2109fa (diff)
downloadtalos-hostboot-644984fb1230696d7990d32b22fd551d9090a862.tar.gz
talos-hostboot-644984fb1230696d7990d32b22fd551d9090a862.zip
Add implementation of ATTR_MSS_MRW_PERIODIC_MEMCAL_MODE_OPTIONS
Note in XML that ATTR_MRW_CLEANER_ENABLE, prefetch is not for Nimbus Note in XML that ATTR_MRW_DRAMINIT_RESET_DISABLE is implemented Add ZQCAL modes Update defaults, etc. per review minutes. Change-Id: I085bfa7d9b868e7676bd22842cf88253dffb1854 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/28152 Tested-by: William G. Hoffa <wghoffa@us.ibm.com> Reviewed-by: William G. Hoffa <wghoffa@us.ibm.com>
Diffstat (limited to 'src/import/chips/p9/procedures/hwp')
-rw-r--r--src/import/chips/p9/procedures/hwp/memory/lib/eff_config/eff_config.C20
-rw-r--r--src/import/chips/p9/procedures/hwp/memory/lib/eff_config/timing.C4
-rw-r--r--src/import/chips/p9/procedures/hwp/memory/lib/mc/port.C57
-rw-r--r--src/import/chips/p9/procedures/hwp/memory/lib/mss_attribute_accessors.H195
-rw-r--r--src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit_training.C5
5 files changed, 171 insertions, 110 deletions
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/eff_config/eff_config.C b/src/import/chips/p9/procedures/hwp/memory/lib/eff_config/eff_config.C
index adc3427e9..546242237 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/eff_config/eff_config.C
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/eff_config/eff_config.C
@@ -484,7 +484,7 @@ fapi2::ReturnCode eff_config::refresh_interval_time(const fapi2::Target<TARGET_T
// Calculates appropriate tREFI based on fine refresh mode
switch(l_refresh_mode)
{
- case fapi2::ENUM_ATTR_MRW_FINE_REFRESH_MODE_NORMAL:
+ case fapi2::ENUM_ATTR_MSS_MRW_FINE_REFRESH_MODE_NORMAL:
FAPI_TRY( calc_trefi( mss::refresh_rate::REF1X,
l_temp_refresh_range,
@@ -492,8 +492,8 @@ fapi2::ReturnCode eff_config::refresh_interval_time(const fapi2::Target<TARGET_T
"Failed to calculate tREF1" );
break;
- case fapi2::ENUM_ATTR_MRW_FINE_REFRESH_MODE_FIXED_2X:
- case fapi2::ENUM_ATTR_MRW_FINE_REFRESH_MODE_FLY_2X:
+ case fapi2::ENUM_ATTR_MSS_MRW_FINE_REFRESH_MODE_FIXED_2X:
+ case fapi2::ENUM_ATTR_MSS_MRW_FINE_REFRESH_MODE_FLY_2X:
FAPI_TRY( calc_trefi( mss::refresh_rate::REF2X,
l_temp_refresh_range,
@@ -501,8 +501,8 @@ fapi2::ReturnCode eff_config::refresh_interval_time(const fapi2::Target<TARGET_T
"Failed to calculate tREF2" );
break;
- case fapi2::ENUM_ATTR_MRW_FINE_REFRESH_MODE_FIXED_4X:
- case fapi2::ENUM_ATTR_MRW_FINE_REFRESH_MODE_FLY_4X:
+ case fapi2::ENUM_ATTR_MSS_MRW_FINE_REFRESH_MODE_FIXED_4X:
+ case fapi2::ENUM_ATTR_MSS_MRW_FINE_REFRESH_MODE_FLY_4X:
FAPI_TRY( calc_trefi( mss::refresh_rate::REF4X,
l_temp_refresh_range,
@@ -579,19 +579,19 @@ fapi2::ReturnCode eff_config::refresh_cycle_time(const fapi2::Target<TARGET_TYPE
// Selects appropriate tRFC based on fine refresh mode
switch(l_refresh_mode)
{
- case fapi2::ENUM_ATTR_MRW_FINE_REFRESH_MODE_NORMAL:
+ case fapi2::ENUM_ATTR_MSS_MRW_FINE_REFRESH_MODE_NORMAL:
FAPI_TRY( iv_pDecoder->min_refresh_recovery_delay_time_1(i_target, l_trfc_mtb),
"Failed to decode SPD for tRFC1" );
break;
- case fapi2::ENUM_ATTR_MRW_FINE_REFRESH_MODE_FIXED_2X:
- case fapi2::ENUM_ATTR_MRW_FINE_REFRESH_MODE_FLY_2X:
+ case fapi2::ENUM_ATTR_MSS_MRW_FINE_REFRESH_MODE_FIXED_2X:
+ case fapi2::ENUM_ATTR_MSS_MRW_FINE_REFRESH_MODE_FLY_2X:
FAPI_TRY( iv_pDecoder->min_refresh_recovery_delay_time_2(i_target, l_trfc_mtb),
"Failed to decode SPD for tRFC2" );
break;
- case fapi2::ENUM_ATTR_MRW_FINE_REFRESH_MODE_FIXED_4X:
- case fapi2::ENUM_ATTR_MRW_FINE_REFRESH_MODE_FLY_4X:
+ case fapi2::ENUM_ATTR_MSS_MRW_FINE_REFRESH_MODE_FIXED_4X:
+ case fapi2::ENUM_ATTR_MSS_MRW_FINE_REFRESH_MODE_FLY_4X:
FAPI_TRY( iv_pDecoder->min_refresh_recovery_delay_time_4(i_target, l_trfc_mtb),
"Failed to decode SPD for tRFC4" );
break;
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/eff_config/timing.C b/src/import/chips/p9/procedures/hwp/memory/lib/eff_config/timing.C
index 7e7f79c57..db75d5b14 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/eff_config/timing.C
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/eff_config/timing.C
@@ -87,11 +87,11 @@ fapi2::ReturnCode calc_trefi( const refresh_rate i_mode,
switch(i_temp_refresh_range)
{
- case fapi2::ENUM_ATTR_MRW_TEMP_REFRESH_RANGE_NORMAL:
+ case fapi2::ENUM_ATTR_MSS_MRW_TEMP_REFRESH_RANGE_NORMAL:
l_multiplier = temp_mode::NORMAL;
break;
- case fapi2::ENUM_ATTR_MRW_TEMP_REFRESH_RANGE_EXTEND:
+ case fapi2::ENUM_ATTR_MSS_MRW_TEMP_REFRESH_RANGE_EXTEND:
l_multiplier = temp_mode::EXTENDED;
break;
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/mc/port.C b/src/import/chips/p9/procedures/hwp/memory/lib/mc/port.C
index 43a5ba1ed..83dd37ad9 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/mc/port.C
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/mc/port.C
@@ -42,6 +42,28 @@
namespace mss
{
+// Bit position settings for ATTR_MSS_MRW_PERIODIC_MEMCAL_MODE_OPTIONS
+// For each bit: OFF = 0, ON = 1
+// Byte 0:
+constexpr uint64_t BIT_ZCAL = 0; // 0: ZCAL
+constexpr uint64_t BIT_SYSCLK_ALIGN = 1; // 1: SYSCK_ALIGN
+constexpr uint64_t BIT_RDCENTERING = 2; // 2: RDCENTERING
+constexpr uint64_t BIT_RDLCK_ALIGN = 3; // 3: RDLCK_ALIGN
+constexpr uint64_t BIT_DQS_ALIGN = 4; // 4: DQS_ALIGN
+constexpr uint64_t BIT_RDCLK_UPDATE = 5; // 5: RDCLK_UPDATE
+constexpr uint64_t BIT_PER_DUTYCYCLE = 6; // 6: PER_DUTYCYCLE
+constexpr uint64_t BIT_PERCAL_PWR_DIS = 7; // 7: PERCAL_PWR_DIS
+
+// Byte 1:
+constexpr uint64_t BIT_PERCAL_REPEAT_0 = 8; // 0: PERCAL_REPEAT
+constexpr uint64_t BIT_PERCAL_REPEAT_1 = 9; // 1: PERCAL_REPEAT
+constexpr uint64_t BIT_PERCAL_REPEAT = 10; // 2: PERCAL_REPEAT
+constexpr uint64_t BIT_SINGLE_BIT_MPR = 11; // 3: SINGLE_BIT_MPR
+constexpr uint64_t BIT_MBA_CFG_0 = 12; // 4: MBA_CFG_0
+constexpr uint64_t BIT_MBA_CFG_1 = 13; // 5: MBA_CFG_1
+constexpr uint64_t BIT_SPARE_6 = 14; // 6: SPARE
+constexpr uint64_t BIT_SPARE_7 = 15; // 7: SPARE
+
///
/// @brief Enable the MC Periodic calibration functionality - MCA specialization
/// @param[in] i_target the target
@@ -54,6 +76,8 @@ fapi2::ReturnCode enable_periodic_cal( const fapi2::Target<fapi2::TARGET_TYPE_MC
uint32_t l_memcal_interval = 0;
uint32_t l_zqcal_interval = 0;
+ fapi2::buffer<uint16_t> l_per_memcal_mode_options = 0;
+ fapi2::buffer<uint16_t> l_per_zqcal_mode_options = 0;
fapi2::buffer<uint64_t> l_periodic_cal_config;
fapi2::buffer<uint64_t> l_phy_zqcal_config;
@@ -69,10 +93,16 @@ fapi2::ReturnCode enable_periodic_cal( const fapi2::Target<fapi2::TARGET_TYPE_MC
FAPI_TRY( mss::eff_memcal_interval(i_target, l_memcal_interval) );
FAPI_TRY( mss::eff_zqcal_interval(i_target, l_zqcal_interval) );
+ FAPI_TRY( mss::mrw_periodic_memcal_mode_options(l_per_memcal_mode_options) );
+ FAPI_INF("mrw_periodic_memcal_mode_options: 0x%02x", l_per_memcal_mode_options);
+
+ FAPI_TRY( mss::mrw_periodic_zqcal_mode_options(l_per_zqcal_mode_options) );
+ FAPI_INF("mrw_periodic_zqcal_mode_options: 0x%02x", l_per_memcal_mode_options);
+
// TODO RTC:155854 We haven't done the work for calculating init cal periods
// in effective config yet, and the MC setup below is hard wired for sim
- FAPI_DBG("memcal interval %dck, zqcal interval %dck", l_memcal_interval, l_zqcal_interval);
+ FAPI_INF("memcal interval %dck, zqcal interval %dck", l_memcal_interval, l_zqcal_interval);
// I think we can do these in any event BRS
{
@@ -97,7 +127,7 @@ fapi2::ReturnCode enable_periodic_cal( const fapi2::Target<fapi2::TARGET_TYPE_MC
}
// ZQCAL
- if (l_zqcal_interval != 0)
+ if (l_per_zqcal_mode_options != 0)
{
std::vector<uint64_t> l_ranks;
@@ -144,7 +174,7 @@ fapi2::ReturnCode enable_periodic_cal( const fapi2::Target<fapi2::TARGET_TYPE_MC
l_periodic_cal_config.writeBit<TT::PER_ENA_ZCAL>(is_sim ? 0 : 1);
// Write the ZQCAL periodic config
- FAPI_DBG("zcal periodic config: 0x%016lx", l_phy_zqcal_config);
+ FAPI_INF("zcal periodic config: 0x%016lx", l_phy_zqcal_config);
FAPI_TRY( mss::putScom(i_target, TT::PHY_ZQCAL_REG, l_phy_zqcal_config) );
// Write the ZQCAL timer reload register
@@ -164,14 +194,14 @@ fapi2::ReturnCode enable_periodic_cal( const fapi2::Target<fapi2::TARGET_TYPE_MC
fapi2::buffer<uint64_t> l_zcal_timer_reload;
l_zcal_timer_reload.insertFromRight<TT::ZCAL_TIMER_RELOAD_VALUE, TT::ZCAL_TIMER_RELOAD_VALUE_LEN>(
is_sim ? (l_zqcal_interval / TT::MAGIC_NUMBER_SIM) + 1 : (l_zqcal_interval / TT::MAGIC_NUMBER_NOT_SIM) + 1);
- FAPI_DBG("zcal timer reload: 0x%016lx", l_zcal_timer_reload);
+ FAPI_INF("zcal timer reload: 0x%016lx", l_zcal_timer_reload);
FAPI_TRY( mss::putScom(i_target, TT::PHY_ZCAL_TIMER_RELOAD_REG, l_zcal_timer_reload) );
}
}
// MEMCAL
- if (l_memcal_interval != 0)
+ if (l_per_memcal_mode_options != 0)
{
// Setup the periodic enable rank pair field in the phy cal config and the mc. This used to be shared
// between the MC and the PHY in Centaur but no longer is - so we write the same data in two registers.
@@ -186,7 +216,7 @@ fapi2::ReturnCode enable_periodic_cal( const fapi2::Target<fapi2::TARGET_TYPE_MC
l_rank_config.setBit(pair);
}
- FAPI_DBG("periodic ranks: 0x%016lx", l_rank_config);
+ FAPI_INF("periodic ranks: 0x%016lx", l_rank_config);
//
// Configure the controller
@@ -240,19 +270,22 @@ fapi2::ReturnCode enable_periodic_cal( const fapi2::Target<fapi2::TARGET_TYPE_MC
// # 48:63 , 0x01D1, any ; # 464 = 114ms @ 1600MHz
// Add the ranks to the phy config
- l_periodic_cal_config.insert<TT::PER_ZCAL_ENA_RANK, TT::PER_ZCAL_ENA_RANK_LEN>(l_rank_config);
+ if (l_per_memcal_mode_options.getBit<BIT_ZCAL>())
+ {
+ l_periodic_cal_config.insert<TT::PER_ZCAL_ENA_RANK, TT::PER_ZCAL_ENA_RANK_LEN>(l_rank_config);
+ }
// If we're in sim, enable the fast-sim mode
l_periodic_cal_config.writeBit<TT::PER_FAST_SIM_CNTR>(is_sim);
- l_periodic_cal_config.setBit<TT::PER_ENA_SYSCLK_ALIGN>();
+ l_periodic_cal_config.writeBit<TT::PER_ENA_SYSCLK_ALIGN>( l_per_memcal_mode_options.getBit<BIT_SYSCLK_ALIGN>() );
// Per John Bialas 5/16: "... periodic read centering does not work ... We are re-evaluating fixing it for DD2"
#ifdef PERIODIC_READ_CENTERING_FIX
- l_periodic_cal_config.setBit<TT::PER_ENA_READ_CTR>();
+ l_periodic_cal_config.writeBit<TT::PER_ENA_READ_CTR>( l_per_memcal_mode_options.getBit<BIT_RDCENTERING>() );
#endif
- l_periodic_cal_config.setBit<TT::PER_ENA_RDCLK_ALIGN>();
- l_periodic_cal_config.setBit<TT::PER_ENA_DQS_ALIGN>();
+ l_periodic_cal_config.writeBit<TT::PER_ENA_RDCLK_ALIGN>(l_per_memcal_mode_options.getBit<BIT_RDLCK_ALIGN>() );
+ l_periodic_cal_config.writeBit<TT::PER_ENA_DQS_ALIGN>( l_per_memcal_mode_options.getBit<BIT_DQS_ALIGN>() );
// Per John Bialas 5/16: "DD2_FIX_DIS should not be asserted, ie. we do want to use the centaur DD2 fixes"
@@ -273,7 +306,7 @@ fapi2::ReturnCode enable_periodic_cal( const fapi2::Target<fapi2::TARGET_TYPE_MC
fapi2::buffer<uint64_t> l_cal_timer_reload;
l_cal_timer_reload.insertFromRight<TT::PC_CAL_TIMER_RELOAD_VALUE, TT::PC_CAL_TIMER_RELOAD_VALUE_LEN>(
is_sim ? (l_memcal_interval / TT::MAGIC_NUMBER_SIM) + 1 : (l_memcal_interval / TT::MAGIC_NUMBER_NOT_SIM) + 1);
- FAPI_DBG("phy cal timer reload: 0x%016lx", l_cal_timer_reload);
+ FAPI_INF("phy cal timer reload: 0x%016lx", l_cal_timer_reload);
FAPI_TRY( mss::putScom(i_target, TT::PHY_CAL_TIMER_RELOAD_REG, l_cal_timer_reload ) );
}
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/mss_attribute_accessors.H b/src/import/chips/p9/procedures/hwp/memory/lib/mss_attribute_accessors.H
index a062eb316..a03734867 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/mss_attribute_accessors.H
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/mss_attribute_accessors.H
@@ -19444,7 +19444,7 @@ fapi_try_exit:
///
-/// @brief ATTR_MRW_SAFEMODE_MEM_THROTTLED_N_COMMANDS_PER_PORT getter
+/// @brief ATTR_MSS_MRW_SAFEMODE_MEM_THROTTLED_N_COMMANDS_PER_PORT getter
/// @param[out] uint32_t& reference to store the value
/// @note Generated by gen_accessors.pl generateParameters (SYSTEM)
/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
@@ -19454,18 +19454,18 @@ fapi_try_exit:
inline fapi2::ReturnCode mrw_safemode_mem_throttled_n_commands_per_port(uint32_t& o_value)
{
- FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MRW_SAFEMODE_MEM_THROTTLED_N_COMMANDS_PER_PORT,
+ FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_MRW_SAFEMODE_MEM_THROTTLED_N_COMMANDS_PER_PORT,
fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>(), o_value) );
return fapi2::current_err;
fapi_try_exit:
- FAPI_ERR("failed accessing ATTR_MRW_SAFEMODE_MEM_THROTTLED_N_COMMANDS_PER_PORT: 0x%lx (system target)",
+ FAPI_ERR("failed accessing ATTR_MSS_MRW_SAFEMODE_MEM_THROTTLED_N_COMMANDS_PER_PORT: 0x%lx (system target)",
uint64_t(fapi2::current_err));
return fapi2::current_err;
}
///
-/// @brief ATTR_MRW_THERMAL_MEMORY_POWER_LIMIT getter
+/// @brief ATTR_MSS_MRW_THERMAL_MEMORY_POWER_LIMIT getter
/// @param[out] uint32_t& reference to store the value
/// @note Generated by gen_accessors.pl generateParameters (SYSTEM)
/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
@@ -19475,18 +19475,18 @@ fapi_try_exit:
inline fapi2::ReturnCode mrw_thermal_memory_power_limit(uint32_t& o_value)
{
- FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MRW_THERMAL_MEMORY_POWER_LIMIT, fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>(),
+ FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_MRW_THERMAL_MEMORY_POWER_LIMIT, fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>(),
o_value) );
return fapi2::current_err;
fapi_try_exit:
- FAPI_ERR("failed accessing ATTR_MRW_THERMAL_MEMORY_POWER_LIMIT: 0x%lx (system target)",
+ FAPI_ERR("failed accessing ATTR_MSS_MRW_THERMAL_MEMORY_POWER_LIMIT: 0x%lx (system target)",
uint64_t(fapi2::current_err));
return fapi2::current_err;
}
///
-/// @brief ATTR_MRW_DIMM_POWER_CURVE_PERCENT_UPLIFT getter
+/// @brief ATTR_MSS_MRW_DIMM_POWER_CURVE_PERCENT_UPLIFT getter
/// @param[out] uint8_t& reference to store the value
/// @note Generated by gen_accessors.pl generateParameters (SYSTEM)
/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
@@ -19496,18 +19496,18 @@ fapi_try_exit:
inline fapi2::ReturnCode mrw_dimm_power_curve_percent_uplift(uint8_t& o_value)
{
- FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MRW_DIMM_POWER_CURVE_PERCENT_UPLIFT, fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>(),
+ FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_MRW_DIMM_POWER_CURVE_PERCENT_UPLIFT, fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>(),
o_value) );
return fapi2::current_err;
fapi_try_exit:
- FAPI_ERR("failed accessing ATTR_MRW_DIMM_POWER_CURVE_PERCENT_UPLIFT: 0x%lx (system target)",
+ FAPI_ERR("failed accessing ATTR_MSS_MRW_DIMM_POWER_CURVE_PERCENT_UPLIFT: 0x%lx (system target)",
uint64_t(fapi2::current_err));
return fapi2::current_err;
}
///
-/// @brief ATTR_MRW_DIMM_POWER_CURVE_PERCENT_UPLIFT_IDLE getter
+/// @brief ATTR_MSS_MRW_DIMM_POWER_CURVE_PERCENT_UPLIFT_IDLE getter
/// @param[out] uint8_t& reference to store the value
/// @note Generated by gen_accessors.pl generateParameters (SYSTEM)
/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
@@ -19518,18 +19518,18 @@ fapi_try_exit:
inline fapi2::ReturnCode mrw_dimm_power_curve_percent_uplift_idle(uint8_t& o_value)
{
- FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MRW_DIMM_POWER_CURVE_PERCENT_UPLIFT_IDLE,
+ FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_MRW_DIMM_POWER_CURVE_PERCENT_UPLIFT_IDLE,
fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>(), o_value) );
return fapi2::current_err;
fapi_try_exit:
- FAPI_ERR("failed accessing ATTR_MRW_DIMM_POWER_CURVE_PERCENT_UPLIFT_IDLE: 0x%lx (system target)",
+ FAPI_ERR("failed accessing ATTR_MSS_MRW_DIMM_POWER_CURVE_PERCENT_UPLIFT_IDLE: 0x%lx (system target)",
uint64_t(fapi2::current_err));
return fapi2::current_err;
}
///
-/// @brief ATTR_MRW_MEM_M_DRAM_CLOCKS getter
+/// @brief ATTR_MSS_MRW_MEM_M_DRAM_CLOCKS getter
/// @param[out] uint32_t& reference to store the value
/// @note Generated by gen_accessors.pl generateParameters (SYSTEM)
/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
@@ -19541,17 +19541,17 @@ fapi_try_exit:
inline fapi2::ReturnCode mrw_mem_m_dram_clocks(uint32_t& o_value)
{
- FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MRW_MEM_M_DRAM_CLOCKS, fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>(), o_value) );
+ FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_MRW_MEM_M_DRAM_CLOCKS, fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>(), o_value) );
return fapi2::current_err;
fapi_try_exit:
- FAPI_ERR("failed accessing ATTR_MRW_MEM_M_DRAM_CLOCKS: 0x%lx (system target)",
+ FAPI_ERR("failed accessing ATTR_MSS_MRW_MEM_M_DRAM_CLOCKS: 0x%lx (system target)",
uint64_t(fapi2::current_err));
return fapi2::current_err;
}
///
-/// @brief ATTR_MRW_MAX_DRAM_DATABUS_UTIL getter
+/// @brief ATTR_MSS_MRW_MAX_DRAM_DATABUS_UTIL getter
/// @param[out] uint32_t& reference to store the value
/// @note Generated by gen_accessors.pl generateParameters (SYSTEM)
/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
@@ -19562,17 +19562,18 @@ fapi_try_exit:
inline fapi2::ReturnCode mrw_max_dram_databus_util(uint32_t& o_value)
{
- FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MRW_MAX_DRAM_DATABUS_UTIL, fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>(), o_value) );
+ FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_MRW_MAX_DRAM_DATABUS_UTIL, fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>(),
+ o_value) );
return fapi2::current_err;
fapi_try_exit:
- FAPI_ERR("failed accessing ATTR_MRW_MAX_DRAM_DATABUS_UTIL: 0x%lx (system target)",
+ FAPI_ERR("failed accessing ATTR_MSS_MRW_MAX_DRAM_DATABUS_UTIL: 0x%lx (system target)",
uint64_t(fapi2::current_err));
return fapi2::current_err;
}
///
-/// @brief ATTR_MRW_MCS_PREFETCH_RETRY_THRESHOLD getter
+/// @brief ATTR_MSS_MRW_MCS_PREFETCH_RETRY_THRESHOLD getter
/// @param[out] uint8_t& reference to store the value
/// @note Generated by gen_accessors.pl generateParameters (SYSTEM)
/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
@@ -19585,18 +19586,18 @@ fapi_try_exit:
inline fapi2::ReturnCode mrw_mcs_prefetch_retry_threshold(uint8_t& o_value)
{
- FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MRW_MCS_PREFETCH_RETRY_THRESHOLD, fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>(),
+ FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_MRW_MCS_PREFETCH_RETRY_THRESHOLD, fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>(),
o_value) );
return fapi2::current_err;
fapi_try_exit:
- FAPI_ERR("failed accessing ATTR_MRW_MCS_PREFETCH_RETRY_THRESHOLD: 0x%lx (system target)",
+ FAPI_ERR("failed accessing ATTR_MSS_MRW_MCS_PREFETCH_RETRY_THRESHOLD: 0x%lx (system target)",
uint64_t(fapi2::current_err));
return fapi2::current_err;
}
///
-/// @brief ATTR_MRW_POWER_CONTROL_REQUESTED getter
+/// @brief ATTR_MSS_MRW_POWER_CONTROL_REQUESTED getter
/// @param[out] uint8_t& reference to store the value
/// @note Generated by gen_accessors.pl generateParameters (SYSTEM)
/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
@@ -19606,17 +19607,18 @@ fapi_try_exit:
inline fapi2::ReturnCode mrw_power_control_requested(uint8_t& o_value)
{
- FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MRW_POWER_CONTROL_REQUESTED, fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>(), o_value) );
+ FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_MRW_POWER_CONTROL_REQUESTED, fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>(),
+ o_value) );
return fapi2::current_err;
fapi_try_exit:
- FAPI_ERR("failed accessing ATTR_MRW_POWER_CONTROL_REQUESTED: 0x%lx (system target)",
+ FAPI_ERR("failed accessing ATTR_MSS_MRW_POWER_CONTROL_REQUESTED: 0x%lx (system target)",
uint64_t(fapi2::current_err));
return fapi2::current_err;
}
///
-/// @brief ATTR_MRW_VMEM_REGULATOR_POWER_LIMIT_PER_DIMM_ADJ_ENABLE getter
+/// @brief ATTR_MSS_MRW_VMEM_REGULATOR_POWER_LIMIT_PER_DIMM_ADJ_ENABLE getter
/// @param[out] uint8_t& reference to store the value
/// @note Generated by gen_accessors.pl generateParameters (SYSTEM)
/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
@@ -19627,18 +19629,18 @@ fapi_try_exit:
inline fapi2::ReturnCode mrw_vmem_regulator_power_limit_per_dimm_adj_enable(uint8_t& o_value)
{
- FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MRW_VMEM_REGULATOR_POWER_LIMIT_PER_DIMM_ADJ_ENABLE,
+ FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_MRW_VMEM_REGULATOR_POWER_LIMIT_PER_DIMM_ADJ_ENABLE,
fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>(), o_value) );
return fapi2::current_err;
fapi_try_exit:
- FAPI_ERR("failed accessing ATTR_MRW_VMEM_REGULATOR_POWER_LIMIT_PER_DIMM_ADJ_ENABLE: 0x%lx (system target)",
+ FAPI_ERR("failed accessing ATTR_MSS_MRW_VMEM_REGULATOR_POWER_LIMIT_PER_DIMM_ADJ_ENABLE: 0x%lx (system target)",
uint64_t(fapi2::current_err));
return fapi2::current_err;
}
///
-/// @brief ATTR_MRW_MAX_NUMBER_DIMMS_POSSIBLE_PER_VMEM_REGULATOR getter
+/// @brief ATTR_MSS_MRW_MAX_NUMBER_DIMMS_POSSIBLE_PER_VMEM_REGULATOR getter
/// @param[out] uint8_t& reference to store the value
/// @note Generated by gen_accessors.pl generateParameters (SYSTEM)
/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
@@ -19649,18 +19651,18 @@ fapi_try_exit:
inline fapi2::ReturnCode mrw_max_number_dimms_possible_per_vmem_regulator(uint8_t& o_value)
{
- FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MRW_MAX_NUMBER_DIMMS_POSSIBLE_PER_VMEM_REGULATOR,
+ FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_MRW_MAX_NUMBER_DIMMS_POSSIBLE_PER_VMEM_REGULATOR,
fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>(), o_value) );
return fapi2::current_err;
fapi_try_exit:
- FAPI_ERR("failed accessing ATTR_MRW_MAX_NUMBER_DIMMS_POSSIBLE_PER_VMEM_REGULATOR: 0x%lx (system target)",
+ FAPI_ERR("failed accessing ATTR_MSS_MRW_MAX_NUMBER_DIMMS_POSSIBLE_PER_VMEM_REGULATOR: 0x%lx (system target)",
uint64_t(fapi2::current_err));
return fapi2::current_err;
}
///
-/// @brief ATTR_MRW_AVDD_OFFSET_DISABLE getter
+/// @brief ATTR_MSS_MRW_AVDD_OFFSET_DISABLE getter
/// @param[out] uint8_t& reference to store the value
/// @note Generated by gen_accessors.pl generateParameters (SYSTEM)
/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
@@ -19670,17 +19672,17 @@ fapi_try_exit:
inline fapi2::ReturnCode mrw_avdd_offset_disable(uint8_t& o_value)
{
- FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MRW_AVDD_OFFSET_DISABLE, fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>(), o_value) );
+ FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_MRW_AVDD_OFFSET_DISABLE, fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>(), o_value) );
return fapi2::current_err;
fapi_try_exit:
- FAPI_ERR("failed accessing ATTR_MRW_AVDD_OFFSET_DISABLE: 0x%lx (system target)",
+ FAPI_ERR("failed accessing ATTR_MSS_MRW_AVDD_OFFSET_DISABLE: 0x%lx (system target)",
uint64_t(fapi2::current_err));
return fapi2::current_err;
}
///
-/// @brief ATTR_MRW_VDD_OFFSET_DISABLE getter
+/// @brief ATTR_MSS_MRW_VDD_OFFSET_DISABLE getter
/// @param[out] uint8_t& reference to store the value
/// @note Generated by gen_accessors.pl generateParameters (SYSTEM)
/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
@@ -19690,17 +19692,17 @@ fapi_try_exit:
inline fapi2::ReturnCode mrw_vdd_offset_disable(uint8_t& o_value)
{
- FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MRW_VDD_OFFSET_DISABLE, fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>(), o_value) );
+ FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_MRW_VDD_OFFSET_DISABLE, fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>(), o_value) );
return fapi2::current_err;
fapi_try_exit:
- FAPI_ERR("failed accessing ATTR_MRW_VDD_OFFSET_DISABLE: 0x%lx (system target)",
+ FAPI_ERR("failed accessing ATTR_MSS_MRW_VDD_OFFSET_DISABLE: 0x%lx (system target)",
uint64_t(fapi2::current_err));
return fapi2::current_err;
}
///
-/// @brief ATTR_MRW_VCS_OFFSET_DISABLE getter
+/// @brief ATTR_MSS_MRW_VCS_OFFSET_DISABLE getter
/// @param[out] uint8_t& reference to store the value
/// @note Generated by gen_accessors.pl generateParameters (SYSTEM)
/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
@@ -19710,17 +19712,17 @@ fapi_try_exit:
inline fapi2::ReturnCode mrw_vcs_offset_disable(uint8_t& o_value)
{
- FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MRW_VCS_OFFSET_DISABLE, fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>(), o_value) );
+ FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_MRW_VCS_OFFSET_DISABLE, fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>(), o_value) );
return fapi2::current_err;
fapi_try_exit:
- FAPI_ERR("failed accessing ATTR_MRW_VCS_OFFSET_DISABLE: 0x%lx (system target)",
+ FAPI_ERR("failed accessing ATTR_MSS_MRW_VCS_OFFSET_DISABLE: 0x%lx (system target)",
uint64_t(fapi2::current_err));
return fapi2::current_err;
}
///
-/// @brief ATTR_MRW_VPP_OFFSET_DISABLE getter
+/// @brief ATTR_MSS_MRW_VPP_OFFSET_DISABLE getter
/// @param[out] uint8_t& reference to store the value
/// @note Generated by gen_accessors.pl generateParameters (SYSTEM)
/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
@@ -19730,17 +19732,17 @@ fapi_try_exit:
inline fapi2::ReturnCode mrw_vpp_offset_disable(uint8_t& o_value)
{
- FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MRW_VPP_OFFSET_DISABLE, fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>(), o_value) );
+ FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_MRW_VPP_OFFSET_DISABLE, fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>(), o_value) );
return fapi2::current_err;
fapi_try_exit:
- FAPI_ERR("failed accessing ATTR_MRW_VPP_OFFSET_DISABLE: 0x%lx (system target)",
+ FAPI_ERR("failed accessing ATTR_MSS_MRW_VPP_OFFSET_DISABLE: 0x%lx (system target)",
uint64_t(fapi2::current_err));
return fapi2::current_err;
}
///
-/// @brief ATTR_MRW_VDDR_OFFSET_DISABLE getter
+/// @brief ATTR_MSS_MRW_VDDR_OFFSET_DISABLE getter
/// @param[out] uint8_t& reference to store the value
/// @note Generated by gen_accessors.pl generateParameters (SYSTEM)
/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
@@ -19750,17 +19752,17 @@ fapi_try_exit:
inline fapi2::ReturnCode mrw_vddr_offset_disable(uint8_t& o_value)
{
- FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MRW_VDDR_OFFSET_DISABLE, fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>(), o_value) );
+ FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_MRW_VDDR_OFFSET_DISABLE, fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>(), o_value) );
return fapi2::current_err;
fapi_try_exit:
- FAPI_ERR("failed accessing ATTR_MRW_VDDR_OFFSET_DISABLE: 0x%lx (system target)",
+ FAPI_ERR("failed accessing ATTR_MSS_MRW_VDDR_OFFSET_DISABLE: 0x%lx (system target)",
uint64_t(fapi2::current_err));
return fapi2::current_err;
}
///
-/// @brief ATTR_MRW_FINE_REFRESH_MODE getter
+/// @brief ATTR_MSS_MRW_FINE_REFRESH_MODE getter
/// @param[out] uint8_t& reference to store the value
/// @note Generated by gen_accessors.pl generateParameters (SYSTEM)
/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
@@ -19770,17 +19772,17 @@ fapi_try_exit:
inline fapi2::ReturnCode mrw_fine_refresh_mode(uint8_t& o_value)
{
- FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MRW_FINE_REFRESH_MODE, fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>(), o_value) );
+ FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_MRW_FINE_REFRESH_MODE, fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>(), o_value) );
return fapi2::current_err;
fapi_try_exit:
- FAPI_ERR("failed accessing ATTR_MRW_FINE_REFRESH_MODE: 0x%lx (system target)",
+ FAPI_ERR("failed accessing ATTR_MSS_MRW_FINE_REFRESH_MODE: 0x%lx (system target)",
uint64_t(fapi2::current_err));
return fapi2::current_err;
}
///
-/// @brief ATTR_MRW_TEMP_REFRESH_RANGE getter
+/// @brief ATTR_MSS_MRW_TEMP_REFRESH_RANGE getter
/// @param[out] uint8_t& reference to store the value
/// @note Generated by gen_accessors.pl generateParameters (SYSTEM)
/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
@@ -19790,58 +19792,59 @@ fapi_try_exit:
inline fapi2::ReturnCode mrw_temp_refresh_range(uint8_t& o_value)
{
- FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MRW_TEMP_REFRESH_RANGE, fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>(), o_value) );
+ FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_MRW_TEMP_REFRESH_RANGE, fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>(), o_value) );
return fapi2::current_err;
fapi_try_exit:
- FAPI_ERR("failed accessing ATTR_MRW_TEMP_REFRESH_RANGE: 0x%lx (system target)",
+ FAPI_ERR("failed accessing ATTR_MSS_MRW_TEMP_REFRESH_RANGE: 0x%lx (system target)",
uint64_t(fapi2::current_err));
return fapi2::current_err;
}
///
-/// @brief ATTR_MRW_DRAMINIT_RESET_DISABLE getter
+/// @brief ATTR_MSS_MRW_RESET_DELAY_BEFORE_CAL getter
/// @param[out] uint8_t& reference to store the value
/// @note Generated by gen_accessors.pl generateParameters (SYSTEM)
/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
-/// @note A disable switch for resetting the phy delay values at the beginning of calling
-/// mss_draminit_training.
+/// @note For resetting the phy delay values at the beginning of calling
+/// mss_draminit_training. YES means the vaules will be
+/// reset.
///
-inline fapi2::ReturnCode mrw_draminit_reset_disable(uint8_t& o_value)
+inline fapi2::ReturnCode mrw_reset_delay_before_cal(uint8_t& o_value)
{
- FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MRW_DRAMINIT_RESET_DISABLE, fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>(), o_value) );
+ FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_MRW_RESET_DELAY_BEFORE_CAL, fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>(),
+ o_value) );
return fapi2::current_err;
fapi_try_exit:
- FAPI_ERR("failed accessing ATTR_MRW_DRAMINIT_RESET_DISABLE: 0x%lx (system target)",
+ FAPI_ERR("failed accessing ATTR_MSS_MRW_RESET_DELAY_BEFORE_CAL: 0x%lx (system target)",
uint64_t(fapi2::current_err));
return fapi2::current_err;
}
///
-/// @brief ATTR_MRW_PREFETCH_ENABLE getter
+/// @brief ATTR_MSS_MRW_PREFETCH_ENABLE getter
/// @param[out] uint8_t& reference to store the value
/// @note Generated by gen_accessors.pl generateParameters (SYSTEM)
/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
-/// @note Value of on or off. Determines if prefetching enabled or not. See chapter 7 of
-/// the Centaur
-/// Workbook.
+/// @note Value of on or off. Determines if prefetching enabled or
+/// not.
///
inline fapi2::ReturnCode mrw_prefetch_enable(uint8_t& o_value)
{
- FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MRW_PREFETCH_ENABLE, fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>(), o_value) );
+ FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_MRW_PREFETCH_ENABLE, fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>(), o_value) );
return fapi2::current_err;
fapi_try_exit:
- FAPI_ERR("failed accessing ATTR_MRW_PREFETCH_ENABLE: 0x%lx (system target)",
+ FAPI_ERR("failed accessing ATTR_MSS_MRW_PREFETCH_ENABLE: 0x%lx (system target)",
uint64_t(fapi2::current_err));
return fapi2::current_err;
}
///
-/// @brief ATTR_MRW_CLEANER_ENABLE getter
+/// @brief ATTR_MSS_MRW_CLEANER_ENABLE getter
/// @param[out] uint8_t& reference to store the value
/// @note Generated by gen_accessors.pl generateParameters (SYSTEM)
/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
@@ -19852,24 +19855,24 @@ fapi_try_exit:
inline fapi2::ReturnCode mrw_cleaner_enable(uint8_t& o_value)
{
- FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MRW_CLEANER_ENABLE, fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>(), o_value) );
+ FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_MRW_CLEANER_ENABLE, fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>(), o_value) );
return fapi2::current_err;
fapi_try_exit:
- FAPI_ERR("failed accessing ATTR_MRW_CLEANER_ENABLE: 0x%lx (system target)",
+ FAPI_ERR("failed accessing ATTR_MSS_MRW_CLEANER_ENABLE: 0x%lx (system target)",
uint64_t(fapi2::current_err));
return fapi2::current_err;
}
///
/// @brief ATTR_MSS_MRW_OFFSET_GPO getter
-/// @param[out] uint8_t& reference to store the value
+/// @param[out] int8_t& reference to store the value
/// @note Generated by gen_accessors.pl generateParameters (SYSTEM)
/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
-/// @note Global Offset in number of
-/// Clocks
+/// @note Global Offset in number of Clocks. Delta from the value calculated or taken from
+/// VPD.
///
-inline fapi2::ReturnCode mrw_offset_gpo(uint8_t& o_value)
+inline fapi2::ReturnCode mrw_offset_gpo(int8_t& o_value)
{
FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_MRW_OFFSET_GPO, fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>(), o_value) );
@@ -19883,13 +19886,14 @@ fapi_try_exit:
///
/// @brief ATTR_MSS_MRW_OFFSET_RLO getter
-/// @param[out] uint8_t& reference to store the value
+/// @param[out] int8_t& reference to store the value
/// @note Generated by gen_accessors.pl generateParameters (SYSTEM)
/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
-/// @note Read Latency Offset in number of
-/// Clocks
+/// @note Read Latency Offset in number of Clocks. Delta from the value calculated or
+/// taken from
+/// VPD.
///
-inline fapi2::ReturnCode mrw_offset_rlo(uint8_t& o_value)
+inline fapi2::ReturnCode mrw_offset_rlo(int8_t& o_value)
{
FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_MRW_OFFSET_RLO, fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>(), o_value) );
@@ -19903,13 +19907,13 @@ fapi_try_exit:
///
/// @brief ATTR_MSS_MRW_OFFSET_WLO getter
-/// @param[out] uint8_t& reference to store the value
+/// @param[out] int8_t& reference to store the value
/// @note Generated by gen_accessors.pl generateParameters (SYSTEM)
/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
/// @note Write Latency Offset in number of
/// Clocks
///
-inline fapi2::ReturnCode mrw_offset_wlo(uint8_t& o_value)
+inline fapi2::ReturnCode mrw_offset_wlo(int8_t& o_value)
{
FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_MRW_OFFSET_WLO, fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>(), o_value) );
@@ -19926,12 +19930,12 @@ fapi_try_exit:
/// @param[out] uint16_t& reference to store the value
/// @note Generated by gen_accessors.pl generateParameters (SYSTEM)
/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
-/// @note Describes the settings for periodic calibration for port 0: Reading left to
+/// @note Describes the settings for periodic calibration for all ports: Reading left to
/// right. (DEFAULT: 0xD90C -> Byte 0(11011001), Byte 1(00001100)) For each bit: OFF
-/// = 0, ON = 1 Byte 0: 0: ZCAL 1: SYSCK_ALIGN 2 :RDCENTERING 3: RDLCK_ALING 4:
-/// DQS_ALIGN 5: RDCLK_UPDATE 6: PER_DUTYCYCLE 7: PERCAL_PWR_DIS Byte 1: 0:
-/// PERCAL_REPEAT 1: PERCAL_REPEAT 2: PERCAL_REPEAT 3: SINGLE_BIT_MPR 4: MBA_CFG_0
-/// 5: MBA_CFG_1 6: SPARE 7:
+/// = 0, ON = 1. Setting to 0 indicates to disable periodic memcal. Byte 0: 0: ZCAL
+/// 1: SYSCK_ALIGN 2: RDCENTERING 3: RDLCK_ALIGN 4: DQS_ALIGN 5: RDCLK_UPDATE 6:
+/// PER_DUTYCYCLE 7: PERCAL_PWR_DIS Byte 1: 0: PERCAL_REPEAT 1: PERCAL_REPEAT 2:
+/// PERCAL_REPEAT 3: SINGLE_BIT_MPR 4: MBA_CFG_0 5: MBA_CFG_1 6: SPARE 7:
/// SPARE
///
inline fapi2::ReturnCode mrw_periodic_memcal_mode_options(uint16_t& o_value)
@@ -19948,6 +19952,29 @@ fapi_try_exit:
}
///
+/// @brief ATTR_MSS_MRW_PERIODIC_ZQCAL_MODE_OPTIONS getter
+/// @param[out] uint16_t& reference to store the value
+/// @note Generated by gen_accessors.pl generateParameters (SYSTEM)
+/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
+/// @note Describes the settings for periodic ZQ calibration for all ports: Reading left
+/// to right. For each bit: OFF = 0, ON = 1. Setting to 0 indicates to disable
+/// periodic zqcal. Byte 0: 0: ZQCAL All others reserved for future
+/// use
+///
+inline fapi2::ReturnCode mrw_periodic_zqcal_mode_options(uint16_t& o_value)
+{
+
+ FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_MRW_PERIODIC_ZQCAL_MODE_OPTIONS, fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>(),
+ o_value) );
+ return fapi2::current_err;
+
+fapi_try_exit:
+ FAPI_ERR("failed accessing ATTR_MSS_MRW_PERIODIC_ZQCAL_MODE_OPTIONS: 0x%lx (system target)",
+ uint64_t(fapi2::current_err));
+ return fapi2::current_err;
+}
+
+///
/// @brief ATTR_MSS_MRW_TSYS_ADR getter
/// @param[out] uint8_t& reference to store the value
/// @note Generated by gen_accessors.pl generateParameters (SYSTEM)
@@ -19994,9 +20021,9 @@ fapi_try_exit:
/// @param[out] uint8_t& reference to store the value
/// @note Generated by gen_accessors.pl generateParameters (SYSTEM)
/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
-/// @note Allows user to manually turn on and off 2N Mode. AUTO feature defaults to Signal
-/// Integrity generated
-/// setting.
+/// @note Allows user to manually turn on and off 2N Mode. AUTO indicates to use Signal
+/// Integrity generated setting (from
+/// VPD).
///
inline fapi2::ReturnCode mrw_dram_2n_mode(uint8_t& o_value)
{
diff --git a/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit_training.C b/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit_training.C
index 49a6cd09b..e1c67caf6 100644
--- a/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit_training.C
+++ b/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit_training.C
@@ -66,7 +66,7 @@ extern "C"
}
uint8_t l_reset_disable = 0;
- FAPI_TRY( mss::mrw_draminit_reset_disable(l_reset_disable) );
+ FAPI_TRY( mss::mrw_reset_delay_before_cal(l_reset_disable) );
// Configure the CCS engine.
{
@@ -153,8 +153,9 @@ extern "C"
// Check to see if we're supposed to reset the delay values before starting training
// don't reset if we're running special training - assumes there's a checkpoint which has valid state.
- if ((l_reset_disable == fapi2::ENUM_ATTR_MRW_DRAMINIT_RESET_DISABLE_ENABLE) && (i_special_training == 0))
+ if ((l_reset_disable == fapi2::ENUM_ATTR_MSS_MRW_RESET_DELAY_BEFORE_CAL_YES) && (i_special_training == 0))
{
+ FAPI_INF("resetting delay values before cal %s", mss::c_str(p));
FAPI_TRY( mss::dp16::reset_delay_values(p, l_pairs) );
}
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