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| author | Joe McGill <jmcgill@us.ibm.com> | 2018-03-26 09:10:49 -0500 |
|---|---|---|
| committer | Daniel M. Crowell <dcrowell@us.ibm.com> | 2018-04-03 14:13:43 -0400 |
| commit | 3a4e19354e06e9ff07a11aac205164ac21a5509d (patch) | |
| tree | b50e182c7da7e1b76daf3ba8fe9e39cf80efc8aa /src/import/chips/p9/procedures/hwp | |
| parent | bd3148541fc2d5d8fdf2901bebbe3f8530d4ceca (diff) | |
| download | talos-hostboot-3a4e19354e06e9ff07a11aac205164ac21a5509d.tar.gz talos-hostboot-3a4e19354e06e9ff07a11aac205164ac21a5509d.zip | |
move xlink psave configuration to SBE
55058 added inits to prime the PPE for xlink psave
the register touched is in the blacklist, so it can't be touched
on slave chips via FSI in the ioe tl SCOM initifle -- this was
triggering HW CI failures
this commit simply shifts the register setup into the SBE,
where it can be performed securely
Change-Id: I57504ccfe4c5f7e71397d11c7468da42ec09f059
CQ: SW421691
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/56252
Reviewed-by: DANIEL C. HOWE <dchowe@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/56257
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Diffstat (limited to 'src/import/chips/p9/procedures/hwp')
| -rw-r--r-- | src/import/chips/p9/procedures/hwp/initfiles/p9_fbc_ioe_tl_scom.C | 19 |
1 files changed, 0 insertions, 19 deletions
diff --git a/src/import/chips/p9/procedures/hwp/initfiles/p9_fbc_ioe_tl_scom.C b/src/import/chips/p9/procedures/hwp/initfiles/p9_fbc_ioe_tl_scom.C index 858a7ca77..75e58ce9d 100644 --- a/src/import/chips/p9/procedures/hwp/initfiles/p9_fbc_ioe_tl_scom.C +++ b/src/import/chips/p9/procedures/hwp/initfiles/p9_fbc_ioe_tl_scom.C @@ -29,12 +29,6 @@ using namespace fapi2; -constexpr uint64_t literal_0b1 = 0b1; -constexpr uint64_t literal_0b00011 = 0b00011; -constexpr uint64_t literal_0b00001 = 0b00001; -constexpr uint64_t literal_0x01 = 0x01; -constexpr uint64_t literal_0xFF = 0xFF; -constexpr uint64_t literal_0b001 = 0b001; constexpr uint64_t literal_0 = 0; constexpr uint64_t literal_0x1 = 0x1; constexpr uint64_t literal_0x20 = 0x20; @@ -102,19 +96,6 @@ fapi2::ReturnCode p9_fbc_ioe_tl_scom(const fapi2::Target<fapi2::TARGET_TYPE_PROC fapi2::ENUM_ATTR_PROC_FABRIC_X_ATTACHED_CHIP_CNFG_TRUE); fapi2::buffer<uint64_t> l_scom_buffer; { - FAPI_TRY(fapi2::getScom( TGT0, 0x501241aull, l_scom_buffer )); - - l_scom_buffer.insert<1, 1, 63, uint64_t>(literal_0b1 ); - l_scom_buffer.insert<2, 1, 63, uint64_t>(literal_0b1 ); - l_scom_buffer.insert<3, 1, 63, uint64_t>(literal_0b1 ); - l_scom_buffer.insert<35, 5, 59, uint64_t>(literal_0b00011 ); - l_scom_buffer.insert<27, 5, 59, uint64_t>(literal_0b00001 ); - l_scom_buffer.insert<16, 8, 56, uint64_t>(literal_0x01 ); - l_scom_buffer.insert<8, 8, 56, uint64_t>(literal_0xFF ); - l_scom_buffer.insert<5, 3, 61, uint64_t>(literal_0b001 ); - FAPI_TRY(fapi2::putScom(TGT0, 0x501241aull, l_scom_buffer)); - } - { FAPI_TRY(fapi2::getScom( TGT0, 0x501340aull, l_scom_buffer )); if (l_def_X0_ENABLED) |
