Adjust STR enter sequence to enable immediate entry

Change-Id: Id6f2e59fbc3feb7cae69e39685b3c183fba6f2a1
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/71532
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Louis Stermole <stermole@us.ibm.com>
Reviewed-by: STEPHEN GLANCY <sglancy@us.ibm.com>
Dev-Ready: STEPHEN GLANCY <sglancy@us.ibm.com>
Reviewed-by: Matt Derksen <mderkse1@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/71537
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>

3 files changed, 69 insertions, 21 deletions

diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/nvdimm_utils.C b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/nvdimm_utils.C
index 2c579a4ef..ecd6039d5 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/nvdimm_utils.C
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/nvdimm_utils.C
@@ -25,7 +25,7 @@
 
 ///
 /// @file nvdimm_utils.C
-/// @brief Subroutines to support nvdimm backup/restore process
+/// @brief Subroutines to support nvdimm restore process.
 ///
 // *HWP HWP Owner: Tsung Yeung <tyeung@us.ibm.com>
 // *HWP HWP Backup: Stephen Glancy <sglancy@us.ibm.com>
@@ -162,17 +162,21 @@ fapi2::ReturnCode self_refresh_entry( const fapi2::Target<fapi2::TARGET_TYPE_MCA
 {
     fapi2::buffer<uint64_t> l_mbarpc0_data, l_mbastr0_data;
 
-    // Step 1 - In MBARPC0Q, disable power domain control, set domain to MAXALL_MINALL,
-    //          and enable minimum domain reduction
+    // Entry time to 0 for immediate entry
+    constexpr uint64_t l_str_entry_time = 0;
+
+    // Step 1 - In MBARPC0Q, disable power domain control, set domain to MAXALL_MIN0,
+    //          and disable minimum domain reduction (allow immediate entry of STR)
     FAPI_TRY(mss::mc::read_mbarpc0(i_target, l_mbarpc0_data));
     mss::mc::set_power_control_min_max_domains_enable( l_mbarpc0_data, mss::states::OFF );
-    mss::mc::set_power_control_min_max_domains( l_mbarpc0_data, mss::min_max_domains::MAXALL_MINALL );
-    mss::mc::set_power_control_min_domain_reduction_enable( l_mbarpc0_data, mss::states::ON );
+    mss::mc::set_power_control_min_max_domains( l_mbarpc0_data, mss::min_max_domains::MAXALL_MIN0 );
+    mss::mc::set_power_control_min_domain_reduction_enable( l_mbarpc0_data, mss::states::OFF );
     FAPI_TRY(mss::mc::write_mbarpc0(i_target, l_mbarpc0_data));
 
     // Step 2 - In MBASTR0Q, enable STR entry
     FAPI_TRY(mss::mc::read_mbastr0(i_target, l_mbastr0_data));
     mss::mc::set_self_time_refresh_enable( l_mbastr0_data, mss::states::ON );
+    mss::mc::set_enter_self_time_refresh_time( l_mbastr0_data, l_str_entry_time );
     FAPI_TRY(mss::mc::write_mbastr0(i_target, l_mbastr0_data));
 
     // Step 3 - In MBARPC0Q, enable power domain control.
@@ -195,23 +199,22 @@ fapi2::ReturnCode self_refresh_exit( const fapi2::Target<fapi2::TARGET_TYPE_MCA>
     fapi2::buffer<uint64_t> l_mbarpc0_data, l_mbastr0_data;
     const auto& l_mcbist = mss::find_target<fapi2::TARGET_TYPE_MCBIST>(i_target);
 
-    // Step 1 - In MBARPC0Q, disable power domain control
+    // Step 1 - In MBARPC0Q, disable power domain control.
     FAPI_TRY(mss::mc::read_mbarpc0(i_target, l_mbarpc0_data));
     mss::mc::set_power_control_min_max_domains_enable( l_mbarpc0_data, mss::states::OFF );
     FAPI_TRY(mss::mc::write_mbarpc0(i_target, l_mbarpc0_data));
 
-    // Step 2 - In MBASTR0Q, disable STR entry
-    FAPI_TRY(mss::mc::read_mbastr0(i_target, l_mbastr0_data));
-    mss::mc::set_self_time_refresh_enable( l_mbastr0_data, mss::states::OFF );
-    FAPI_TRY(mss::mc::write_mbastr0(i_target, l_mbastr0_data));
-
-    // Step 3 - Run memdiags to read the port to force CKE back to high
+    // Step 2 - Run memdiags to read the port to force CKE back to high
     FAPI_TRY(self_refresh_exit_helper(i_target));
 
     // maint_addr_mode could be enabled by the helper. Disable it before exiting
     // otherwise it will introduce problem to other DIMMs on the same MCBIST
     FAPI_TRY(maint_addr_mode_off(l_mcbist));
 
+    // Restore MBASTR0Q and MBARPC0Q to the original values based on MRW
+    FAPI_TRY(mss::mc::set_pwr_cntrl_reg(i_target));
+    FAPI_TRY(mss::mc::set_str_reg(i_target));
+
 fapi_try_exit:
     return fapi2::current_err;
 }
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/mc/mc.H b/src/import/chips/p9/procedures/hwp/memory/lib/mc/mc.H
index 5f285f159..fdef40a8d 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/mc/mc.H
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/mc/mc.H
@@ -5,7 +5,7 @@
 /*                                                                        */
 /* OpenPOWER HostBoot Project                                             */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2016,2018                        */
+/* Contributors Listed Below - COPYRIGHT 2016,2019                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
 /*                                                                        */
@@ -379,6 +379,34 @@ inline void get_self_time_refresh_enable( const fapi2::buffer<uint64_t>& i_data,
 }
 
 ///
+/// @brief Sets the enter STR time
+/// @tparam T fapi2 Target Type - defaults to TARGET_TYPE_MCA
+/// @tparam TT traits type defaults to mcTraits<T>
+/// @param[in,out] io_data the value of the register
+/// @param[in] i_value the value to write to set the STR time
+///
+template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCA, typename TT = mcTraits<T> >
+inline void set_enter_self_time_refresh_time( fapi2::buffer<uint64_t>& io_data, const uint64_t& i_value )
+{
+    FAPI_DBG("set_enter_self_time_refresh_time to %d", i_value);
+    io_data.insertFromRight<TT::ENTER_STR_TIME_POS, TT::ENTER_STR_TIME_LEN>(i_value);
+}
+
+///
+/// @brief Gets the enter STR time
+/// @tparam T fapi2 Target Type - defaults to TARGET_TYPE_MCA
+/// @tparam TT traits type defaults to mcTraits<T>
+/// @param[in] i_data the value of the register
+/// @param[out] o_value the STR time value from register data
+///
+template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCA, typename TT = mcTraits<T> >
+inline void get_enter_self_time_refresh_time( const fapi2::buffer<uint64_t>& i_data, uint64_t& o_value )
+{
+    o_value = i_data.extractToRight<TT::ENTER_STR_TIME_POS, TT::ENTER_STR_TIME_LEN>();
+    FAPI_DBG("get_enter_self_time_refresh_time %d", o_value);
+}
+
+///
 /// @brief set the PWR CNTRL register
 /// @param[in] i_target the mca target
 /// @return fapi2::fapi2_rc_success if ok
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/workarounds/nvdimm_workarounds.C b/src/import/chips/p9/procedures/hwp/memory/lib/workarounds/nvdimm_workarounds.C
index a544a193a..99fb48cee 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/workarounds/nvdimm_workarounds.C
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/workarounds/nvdimm_workarounds.C
@@ -32,7 +32,7 @@
 // *HWP HWP Backup: Stephen Glancy <sglancy@us.ibm.com>
 // *HWP Team: Memory
 // *HWP Level: 3
-// *HWP Consumed by: FSP:HB
+// *HWP Consumed by: FSP:SBE
 
 #include <fapi2.H>
 #include <vector>
@@ -89,6 +89,13 @@ const uint64_t FARB5Q_REG[] =
     MCA_7_MBA_FARB5Q,
 };
 
+// MCB_CNTLQ
+constexpr const uint64_t MCB_CNTLQ_REG[] =
+{
+    MCBIST_0_MCB_CNTLQ,
+    MCBIST_1_MCB_CNTLQ,
+};
+
 constexpr uint8_t PORTS_PER_MODULE = 8;
 
 ///
@@ -111,22 +118,32 @@ fapi2::ReturnCode self_refresh_entry( const fapi2::Target<fapi2::TARGET_TYPE_PRO
     FAPI_DBG("Entering STR on port %u.", l_mca_pos);
 
     {
-        fapi2::buffer<uint64_t> l_mbarpc0_data, l_mbastr0_data;
+        fapi2::buffer<uint64_t> l_mbarpc0_data, l_mbastr0_data, l_mcbcntlq_data;
         constexpr uint64_t ENABLE = 1;
         constexpr uint64_t DISABLE = 0;
-        constexpr uint64_t MINALL_MAXALL = 0b000;
-
-        // Step 1 - In MBARPC0Q, disable power domain control, set domain to MAXALL_MINALL,
-        //          and enable minimum domain reduction
+        constexpr uint64_t MAXALL_MIN0 = 0b010;
+        constexpr uint64_t STOP = 1;
+        constexpr uint64_t PORTS_PER_MCBIST = 4;
+        constexpr uint64_t TIME_0 = 0;
+        const uint8_t l_mcbist = l_mca_pos < PORTS_PER_MCBIST ? 0 : 1;
+
+        // Stop mcbist first otherwise it can kick the DIMM out of STR
+        FAPI_TRY(fapi2::getScom(i_target, MCB_CNTLQ_REG[l_mcbist], l_mcbcntlq_data));
+        l_mcbcntlq_data.writeBit<MCBIST_CCS_CNTLQ_STOP>(STOP);
+        FAPI_TRY(fapi2::putScom(i_target, MCB_CNTLQ_REG[l_mcbist], l_mcbcntlq_data));
+
+        // Step 1 - In MBARPC0Q, disable power domain control, set domain to MAXALL_MIN0,
+        //          and disable minimum domain reduction (allow immediate entry of STR)
         FAPI_TRY(fapi2::getScom(i_target, MBARPC0Q_REG[l_mca_pos], l_mbarpc0_data));
         l_mbarpc0_data.writeBit<MCA_MBARPC0Q_CFG_MIN_MAX_DOMAINS_ENABLE>(DISABLE);
-        l_mbarpc0_data.insertFromRight<MCA_MBARPC0Q_CFG_MIN_MAX_DOMAINS, MCA_MBARPC0Q_CFG_MIN_MAX_DOMAINS_LEN>(MINALL_MAXALL);
-        l_mbarpc0_data.writeBit<MCA_MBARPC0Q_CFG_MIN_DOMAIN_REDUCTION_ENABLE>(ENABLE);
+        l_mbarpc0_data.insertFromRight<MCA_MBARPC0Q_CFG_MIN_MAX_DOMAINS, MCA_MBARPC0Q_CFG_MIN_MAX_DOMAINS_LEN>(MAXALL_MIN0);
+        l_mbarpc0_data.writeBit<MCA_MBARPC0Q_CFG_MIN_DOMAIN_REDUCTION_ENABLE>(DISABLE);
         FAPI_TRY(fapi2::putScom(i_target, MBARPC0Q_REG[l_mca_pos], l_mbarpc0_data));
 
         // Step 2 - In MBASTR0Q, enable STR entry
         FAPI_TRY(fapi2::getScom(i_target, MBASTR0Q_REG[l_mca_pos], l_mbastr0_data));
         l_mbastr0_data.writeBit<MCA_MBASTR0Q_CFG_STR_ENABLE>(ENABLE);
+        l_mbastr0_data.insertFromRight<MCA_MBASTR0Q_CFG_ENTER_STR_TIME, MCA_MBASTR0Q_CFG_ENTER_STR_TIME_LEN>(TIME_0);
         FAPI_TRY(fapi2::putScom(i_target, MBASTR0Q_REG[l_mca_pos], l_mbastr0_data));
 
         // Step 3 - In MBARPC0Q, enable power domain control.