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author | Li Meng <shlimeng@cn.ibm.com> | 2018-12-13 02:58:37 -0600 |
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committer | Christian R. Geddes <crgeddes@us.ibm.com> | 2019-02-12 22:42:04 -0600 |
commit | 92878a72ccf2ae569e4d159f5d0d05511200108c (patch) | |
tree | 07b186d28350e7dc43b9b9e469dbc9fb75e8dedb /src/import/chips/p9/procedures/hwp | |
parent | 72a52820278d033d28c5f97072bd198b2f25da66 (diff) | |
download | talos-hostboot-92878a72ccf2ae569e4d159f5d0d05511200108c.tar.gz talos-hostboot-92878a72ccf2ae569e4d159f5d0d05511200108c.zip |
Adds some BCW safe delay for LRDIMM
Change-Id: Ida8101737e39e040009fa6fb3c2a6b36b85bed6e
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/69751
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: STEPHEN GLANCY <sglancy@us.ibm.com>
Reviewed-by: Louis Stermole <stermole@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/69857
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>
Diffstat (limited to 'src/import/chips/p9/procedures/hwp')
-rw-r--r-- | src/import/chips/p9/procedures/hwp/memory/lib/dimm/bcw_load_ddr4.C | 8 |
1 files changed, 5 insertions, 3 deletions
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/bcw_load_ddr4.C b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/bcw_load_ddr4.C index 78a9a7676..8fbf74623 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/bcw_load_ddr4.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/bcw_load_ddr4.C @@ -68,6 +68,8 @@ namespace mss fapi2::ReturnCode bcw_load_ddr4( const fapi2::Target<TARGET_TYPE_DIMM>& i_target, std::vector< ccs::instruction_t<TARGET_TYPE_MCBIST> >& io_inst) { + constexpr uint64_t SAFE_DELAY = 2000; // Waiting a safe amount of time as the LRDIMM spec + // doesn't give us an explicit value for this delay FAPI_INF("bcw_load_ddr4 %s", mss::c_str(i_target) ); uint8_t l_sim = 0; @@ -115,7 +117,7 @@ fapi2::ReturnCode bcw_load_ddr4( const fapi2::Target<TARGET_TYPE_DIMM>& i_target // 8-bit BCW's now // Function space 0 - we're already there, so that's nice { FUNC_SPACE_0, BUFF_CONFIG_CW, eff_dimm_ddr4_f0bc1x, mss::tmrc(), CW8_DATA_LEN, cw_info::BCW}, - { FUNC_SPACE_0, LRDIMM_OPERATING_SPEED, eff_dimm_ddr4_f0bc6x, mss::tmrc(), CW8_DATA_LEN, cw_info::BCW}, + { FUNC_SPACE_0, LRDIMM_OPERATING_SPEED, eff_dimm_ddr4_f0bc6x, SAFE_DELAY, CW8_DATA_LEN, cw_info::BCW}, // Function space 2 { FUNC_SPACE_2, FUNC_SPACE_SELECT_CW, FUNC_SPACE_2, mss::tmrd(), CW8_DATA_LEN, cw_info::BCW}, @@ -123,8 +125,8 @@ fapi2::ReturnCode bcw_load_ddr4( const fapi2::Target<TARGET_TYPE_DIMM>& i_target // Function space 5 { FUNC_SPACE_5, FUNC_SPACE_SELECT_CW, FUNC_SPACE_5, mss::tmrd(), CW8_DATA_LEN, cw_info::BCW}, - { FUNC_SPACE_5, HOST_VREF_CW, eff_dimm_ddr4_f5bc5x, mss::lrdimm::vref_time_long(i_target), CW8_DATA_LEN, cw_info::BCW}, - { FUNC_SPACE_5, DRAM_VREF_CW, eff_dimm_ddr4_f5bc6x, mss::lrdimm::vref_time_long(i_target), CW8_DATA_LEN, cw_info::BCW}, + { FUNC_SPACE_5, HOST_VREF_CW, eff_dimm_ddr4_f5bc5x, SAFE_DELAY, CW8_DATA_LEN, cw_info::BCW}, + { FUNC_SPACE_5, DRAM_VREF_CW, eff_dimm_ddr4_f5bc6x, SAFE_DELAY, CW8_DATA_LEN, cw_info::BCW}, // Function space 6 { FUNC_SPACE_6, FUNC_SPACE_SELECT_CW, FUNC_SPACE_6, mss::tmrd(), CW8_DATA_LEN, cw_info::BCW}, |