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| author | Joe McGill <jmcgill@us.ibm.com> | 2018-06-11 17:02:08 -0500 |
|---|---|---|
| committer | Christian R. Geddes <crgeddes@us.ibm.com> | 2019-04-10 12:15:12 -0500 |
| commit | 834bc3db0d21208bc353b44ced9ac75a9888cce9 (patch) | |
| tree | bd54f72fee1ac7779293ba9897d85a0c59d5c8d5 /src/import/chips/p9/procedures/hwp | |
| parent | 1b7cc09d2da589de02e22d4a502492441c50c5a2 (diff) | |
| download | talos-hostboot-834bc3db0d21208bc353b44ced9ac75a9888cce9.tar.gz talos-hostboot-834bc3db0d21208bc353b44ced9ac75a9888cce9.zip | |
shift OBUS FIR programming inits for secure boot
p9_sbe_scominit:
unmask all OBUS EXTFIR bits, use PB CENT FIR 14 to mark update
for downstream code (qualify XBUS/OBUS EXTFIR updates to apply to PPE
platform only)
p9_fab_iovalid:
conditionally unmask OBUS EXTFIR based on state of PB CENT FIR 14
(will handle unmasking here when insecure -- Cronus or old SBE images)
p9_obus_extfir_setup:
new HWP for HB to call, mask OBUS EXTFIR bits for unused busses
Change-Id: I87cf6cf3e73130c6f5a61514da7350262358c91c
Original-Change-Id: I07e7da4a7c61c041451ff4ddfeec3c266385d404
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/60358
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Thi N. Tran <thi@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/75757
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>
Diffstat (limited to 'src/import/chips/p9/procedures/hwp')
| -rw-r--r-- | src/import/chips/p9/procedures/hwp/nest/p9_xbus_fir_utils.H | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/import/chips/p9/procedures/hwp/nest/p9_xbus_fir_utils.H b/src/import/chips/p9/procedures/hwp/nest/p9_xbus_fir_utils.H index f5d5fdcf9..e21d9d981 100644 --- a/src/import/chips/p9/procedures/hwp/nest/p9_xbus_fir_utils.H +++ b/src/import/chips/p9/procedures/hwp/nest/p9_xbus_fir_utils.H @@ -62,7 +62,7 @@ const uint32_t X_PG_PBIOX2_REGION_BIT = 11; // one register per chip (encompassing all links), in N3 chiplet const uint64_t FBC_EXT_FIR_ACTION0 = 0x0000000000000000ULL; const uint64_t FBC_EXT_FIR_ACTION1 = 0x0000000000000000ULL; -const uint64_t FBC_EXT_FIR_MASK = 0x1F00000000000000ULL; +const uint64_t FBC_EXT_FIR_MASK = 0x0100000000000000ULL; const uint64_t FBC_EXT_FIR_MASK_X0_NF = 0x8000000000000000ULL; const uint64_t FBC_EXT_FIR_MASK_X1_NF = 0x4000000000000000ULL; |
