Revert "P9 Xbus/DMI CM Workaround"

This reverts commit 20cda0435fc199da99ca47ab654360ec884c721c.

Change-Id: I916d22b6ea3d32c50b9c8b4481362d16919c4897
CQ: SW461582
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/75333
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/75358
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Reviewed-by: William G. Hoffa <wghoffa@us.ibm.com>

6 files changed, 25 insertions, 128 deletions

diff --git a/src/import/chips/p9/procedures/hwp/initfiles/p9_xbus_g0_scom.C b/src/import/chips/p9/procedures/hwp/initfiles/p9_xbus_g0_scom.C
index 627a74c20..1442041f7 100644
--- a/src/import/chips/p9/procedures/hwp/initfiles/p9_xbus_g0_scom.C
+++ b/src/import/chips/p9/procedures/hwp/initfiles/p9_xbus_g0_scom.C
@@ -43,12 +43,12 @@ constexpr uint64_t literal_0b0000011 = 0b0000011;
 constexpr uint64_t literal_0b000000 = 0b000000;
 constexpr uint64_t literal_0b100111 = 0b100111;
 constexpr uint64_t literal_0b1010 = 0b1010;
-constexpr uint64_t literal_0b00 = 0b00;
+constexpr uint64_t literal_0b01 = 0b01;
 constexpr uint64_t literal_0b11 = 0b11;
-constexpr uint64_t literal_0b01010000 = 0b01010000;
 constexpr uint64_t literal_0b01011100 = 0b01011100;
-constexpr uint64_t literal_0b00110111 = 0b00110111;
+constexpr uint64_t literal_0b01100110 = 0b01100110;
 constexpr uint64_t literal_0b00111101 = 0b00111101;
+constexpr uint64_t literal_0b01000100 = 0b01000100;
 constexpr uint64_t literal_0b0010000 = 0b0010000;
 constexpr uint64_t literal_0b00001 = 0b00001;
 constexpr uint64_t literal_0b0001 = 0b0001;
@@ -61,7 +61,7 @@ constexpr uint64_t literal_0b0000000000000000 = 0b0000000000000000;
 constexpr uint64_t literal_0b01111111 = 0b01111111;
 constexpr uint64_t literal_0b10 = 0b10;
 constexpr uint64_t literal_0b1100 = 0b1100;
-constexpr uint64_t literal_0b01 = 0b01;
+constexpr uint64_t literal_0b00 = 0b00;
 constexpr uint64_t literal_0b01110 = 0b01110;
 
 fapi2::ReturnCode p9_xbus_g0_scom(const fapi2::Target<fapi2::TARGET_TYPE_XBUS>& TGT0,
@@ -3213,7 +3213,7 @@ fapi2::ReturnCode p9_xbus_g0_scom(const fapi2::Target<fapi2::TARGET_TYPE_XBUS>&
         {
             FAPI_TRY(fapi2::getScom( TGT0, 0x8008c00006010c3full, l_scom_buffer ));
 
-            l_scom_buffer.insert<48, 2, 62, uint64_t>(literal_0b00 );
+            l_scom_buffer.insert<48, 2, 62, uint64_t>(literal_0b01 );
             constexpr auto l_IOF1_RX_RX0_RXCTL_CTL_REGS_RX_CTL_REGS_RX_PEAK_TUNE_OFF = 0x0;
             l_scom_buffer.insert<55, 1, 63, uint64_t>(l_IOF1_RX_RX0_RXCTL_CTL_REGS_RX_CTL_REGS_RX_PEAK_TUNE_OFF );
             l_scom_buffer.insert<57, 2, 62, uint64_t>(literal_0b11 );
@@ -3240,20 +3240,20 @@ fapi2::ReturnCode p9_xbus_g0_scom(const fapi2::Target<fapi2::TARGET_TYPE_XBUS>&
 
             if ((l_TGT0_ATTR_IO_XBUS_CHAN_EQ & ENUM_ATTR_IO_XBUS_CHAN_EQ_LOWER_VGA_GAIN_TARGET))
             {
-                l_scom_buffer.insert<48, 8, 56, uint64_t>(literal_0b01010000 );
+                l_scom_buffer.insert<48, 8, 56, uint64_t>(literal_0b01011100 );
             }
             else if (( true ))
             {
-                l_scom_buffer.insert<48, 8, 56, uint64_t>(literal_0b01011100 );
+                l_scom_buffer.insert<48, 8, 56, uint64_t>(literal_0b01100110 );
             }
 
             if ((l_TGT0_ATTR_IO_XBUS_CHAN_EQ & ENUM_ATTR_IO_XBUS_CHAN_EQ_LOWER_VGA_GAIN_TARGET))
             {
-                l_scom_buffer.insert<56, 8, 56, uint64_t>(literal_0b00110111 );
+                l_scom_buffer.insert<56, 8, 56, uint64_t>(literal_0b00111101 );
             }
             else if (( true ))
             {
-                l_scom_buffer.insert<56, 8, 56, uint64_t>(literal_0b00111101 );
+                l_scom_buffer.insert<56, 8, 56, uint64_t>(literal_0b01000100 );
             }
 
             FAPI_TRY(fapi2::putScom(TGT0, 0x8008d00006010c3full, l_scom_buffer));
@@ -3377,7 +3377,6 @@ fapi2::ReturnCode p9_xbus_g0_scom(const fapi2::Target<fapi2::TARGET_TYPE_XBUS>&
 
             constexpr auto l_IOF1_RX_RX0_RXCTL_DATASM_DATASM_REGS_RX_CTL_DATASM_CLKDIST_PDWN_OFF = 0x0;
             l_scom_buffer.insert<60, 1, 63, uint64_t>(l_IOF1_RX_RX0_RXCTL_DATASM_DATASM_REGS_RX_CTL_DATASM_CLKDIST_PDWN_OFF );
-            l_scom_buffer.insert<56, 4, 60, uint64_t>(literal_0b0010 );
             FAPI_TRY(fapi2::putScom(TGT0, 0x800b800006010c3full, l_scom_buffer));
         }
         {
diff --git a/src/import/chips/p9/procedures/hwp/initfiles/p9_xbus_g1_scom.C b/src/import/chips/p9/procedures/hwp/initfiles/p9_xbus_g1_scom.C
index 43487aa9c..c8052a2ca 100644
--- a/src/import/chips/p9/procedures/hwp/initfiles/p9_xbus_g1_scom.C
+++ b/src/import/chips/p9/procedures/hwp/initfiles/p9_xbus_g1_scom.C
@@ -44,12 +44,12 @@ constexpr uint64_t literal_0b000000 = 0b000000;
 constexpr uint64_t literal_0b100111 = 0b100111;
 constexpr uint64_t literal_0b000001 = 0b000001;
 constexpr uint64_t literal_0b1010 = 0b1010;
-constexpr uint64_t literal_0b00 = 0b00;
+constexpr uint64_t literal_0b01 = 0b01;
 constexpr uint64_t literal_0b11 = 0b11;
-constexpr uint64_t literal_0b01010000 = 0b01010000;
 constexpr uint64_t literal_0b01011100 = 0b01011100;
-constexpr uint64_t literal_0b00110111 = 0b00110111;
+constexpr uint64_t literal_0b01100110 = 0b01100110;
 constexpr uint64_t literal_0b00111101 = 0b00111101;
+constexpr uint64_t literal_0b01000100 = 0b01000100;
 constexpr uint64_t literal_0b0010000 = 0b0010000;
 constexpr uint64_t literal_0b00001 = 0b00001;
 constexpr uint64_t literal_0b0001 = 0b0001;
@@ -62,7 +62,7 @@ constexpr uint64_t literal_0b0000000000000000 = 0b0000000000000000;
 constexpr uint64_t literal_0b01111111 = 0b01111111;
 constexpr uint64_t literal_0b10 = 0b10;
 constexpr uint64_t literal_0b1100 = 0b1100;
-constexpr uint64_t literal_0b01 = 0b01;
+constexpr uint64_t literal_0b00 = 0b00;
 constexpr uint64_t literal_0b01110 = 0b01110;
 
 fapi2::ReturnCode p9_xbus_g1_scom(const fapi2::Target<fapi2::TARGET_TYPE_XBUS>& TGT0,
@@ -3214,7 +3214,7 @@ fapi2::ReturnCode p9_xbus_g1_scom(const fapi2::Target<fapi2::TARGET_TYPE_XBUS>&
         {
             FAPI_TRY(fapi2::getScom( TGT0, 0x8008c02006010c3full, l_scom_buffer ));
 
-            l_scom_buffer.insert<48, 2, 62, uint64_t>(literal_0b00 );
+            l_scom_buffer.insert<48, 2, 62, uint64_t>(literal_0b01 );
             constexpr auto l_IOF1_RX_RX1_RXCTL_CTL_REGS_RX_CTL_REGS_RX_PEAK_TUNE_OFF = 0x0;
             l_scom_buffer.insert<55, 1, 63, uint64_t>(l_IOF1_RX_RX1_RXCTL_CTL_REGS_RX_CTL_REGS_RX_PEAK_TUNE_OFF );
             l_scom_buffer.insert<57, 2, 62, uint64_t>(literal_0b11 );
@@ -3241,20 +3241,20 @@ fapi2::ReturnCode p9_xbus_g1_scom(const fapi2::Target<fapi2::TARGET_TYPE_XBUS>&
 
             if ((l_TGT0_ATTR_IO_XBUS_CHAN_EQ & ENUM_ATTR_IO_XBUS_CHAN_EQ_LOWER_VGA_GAIN_TARGET))
             {
-                l_scom_buffer.insert<48, 8, 56, uint64_t>(literal_0b01010000 );
+                l_scom_buffer.insert<48, 8, 56, uint64_t>(literal_0b01011100 );
             }
             else if (( true ))
             {
-                l_scom_buffer.insert<48, 8, 56, uint64_t>(literal_0b01011100 );
+                l_scom_buffer.insert<48, 8, 56, uint64_t>(literal_0b01100110 );
             }
 
             if ((l_TGT0_ATTR_IO_XBUS_CHAN_EQ & ENUM_ATTR_IO_XBUS_CHAN_EQ_LOWER_VGA_GAIN_TARGET))
             {
-                l_scom_buffer.insert<56, 8, 56, uint64_t>(literal_0b00110111 );
+                l_scom_buffer.insert<56, 8, 56, uint64_t>(literal_0b00111101 );
             }
             else if (( true ))
             {
-                l_scom_buffer.insert<56, 8, 56, uint64_t>(literal_0b00111101 );
+                l_scom_buffer.insert<56, 8, 56, uint64_t>(literal_0b01000100 );
             }
 
             FAPI_TRY(fapi2::putScom(TGT0, 0x8008d02006010c3full, l_scom_buffer));
@@ -3378,7 +3378,6 @@ fapi2::ReturnCode p9_xbus_g1_scom(const fapi2::Target<fapi2::TARGET_TYPE_XBUS>&
 
             constexpr auto l_IOF1_RX_RX1_RXCTL_DATASM_DATASM_REGS_RX_CTL_DATASM_CLKDIST_PDWN_OFF = 0x0;
             l_scom_buffer.insert<60, 1, 63, uint64_t>(l_IOF1_RX_RX1_RXCTL_DATASM_DATASM_REGS_RX_CTL_DATASM_CLKDIST_PDWN_OFF );
-            l_scom_buffer.insert<56, 4, 60, uint64_t>(literal_0b0010 );
             FAPI_TRY(fapi2::putScom(TGT0, 0x800b802006010c3full, l_scom_buffer));
         }
         {
diff --git a/src/import/chips/p9/procedures/hwp/initfiles/p9c_dmi_io_scom.C b/src/import/chips/p9/procedures/hwp/initfiles/p9c_dmi_io_scom.C
index d65aeca70..259e82fed 100644
--- a/src/import/chips/p9/procedures/hwp/initfiles/p9c_dmi_io_scom.C
+++ b/src/import/chips/p9/procedures/hwp/initfiles/p9c_dmi_io_scom.C
@@ -54,8 +54,6 @@ constexpr uint64_t literal_7 = 7;
 constexpr uint64_t literal_0b1010 = 0b1010;
 constexpr uint64_t literal_0b01 = 0b01;
 constexpr uint64_t literal_0b00 = 0b00;
-constexpr uint64_t literal_0b01010000 = 0b01010000;
-constexpr uint64_t literal_0b00110111 = 0b00110111;
 constexpr uint64_t literal_0b0010111 = 0b0010111;
 constexpr uint64_t literal_0b00010 = 0b00010;
 constexpr uint64_t literal_0b0010 = 0b0010;
@@ -4241,13 +4239,6 @@ fapi2::ReturnCode p9c_dmi_io_scom(const fapi2::Target<fapi2::TARGET_TYPE_DMI>& T
             FAPI_TRY(fapi2::putScom(TGT0, 0x8008c0600701103full, l_scom_buffer));
         }
         {
-            FAPI_TRY(fapi2::getScom( TGT0, 0x8008d0600701103full, l_scom_buffer ));
-
-            l_scom_buffer.insert<48, 8, 56, uint64_t>(literal_0b01010000 );
-            l_scom_buffer.insert<56, 8, 56, uint64_t>(literal_0b00110111 );
-            FAPI_TRY(fapi2::putScom(TGT0, 0x8008d0600701103full, l_scom_buffer));
-        }
-        {
             FAPI_TRY(fapi2::getScom( TGT0, 0x800970600701103full, l_scom_buffer ));
 
             constexpr auto l_IOMP_RX3_RXCTL_CTL_REGS_RX_CTL_REGS_RX_RC_ENABLE_CTLE_1ST_LATCH_OFFSET_CAL_ON = 0x1;
@@ -4368,7 +4359,6 @@ fapi2::ReturnCode p9c_dmi_io_scom(const fapi2::Target<fapi2::TARGET_TYPE_DMI>& T
             l_scom_buffer.insert<60, 1, 63, uint64_t>(l_IOMP_RX3_RXCTL_DATASM_DATASM_REGS_RX_CTL_DATASM_CLKDIST_PDWN_OFF );
             constexpr auto l_IOMP_RX3_RXCTL_DATASM_DATASM_REGS_RX_PG_DATASM_SPARE_MODE_0_ON = 0x1;
             l_scom_buffer.insert<48, 1, 63, uint64_t>(l_IOMP_RX3_RXCTL_DATASM_DATASM_REGS_RX_PG_DATASM_SPARE_MODE_0_ON );
-            l_scom_buffer.insert<56, 4, 60, uint64_t>(literal_0b0010 );
             FAPI_TRY(fapi2::putScom(TGT0, 0x800b80600701103full, l_scom_buffer));
         }
         {
diff --git a/src/import/chips/p9/procedures/hwp/io/p9_io_dmi_dccal.C b/src/import/chips/p9/procedures/hwp/io/p9_io_dmi_dccal.C
index 1fca10682..dd255cbd3 100644
--- a/src/import/chips/p9/procedures/hwp/io/p9_io_dmi_dccal.C
+++ b/src/import/chips/p9/procedures/hwp/io/p9_io_dmi_dccal.C
@@ -663,54 +663,6 @@ fapi_try_exit:
 }
 
 /**
- * @brief P9 Rx Xbus Override Common Mode Settings :: SW446658
- * @param[in] i_tgt    FAPI2 Target
- * @retval ReturnCode
- */
-fapi2::ReturnCode p9_dmi_override_cm(const DMI_TGT i_tgt)
-{
-    const uint8_t XBUS_LANES = 17;
-    const uint8_t GRP3       =  3;
-    const uint8_t LANE_00    =  0;
-    uint64_t      l_data     =  0;
-    uint64_t      l_cmcrs    =  0;
-
-    FAPI_IMP("p9_dmi_override_cm: I/O EDI+ Xbus Entering");
-
-    // Set CMDAC = 2->5. This is needed to keep the common mode at the
-    //   sampling latch equivalent
-    FAPI_TRY(io::rmw(EDIP_RX_PG_SPARE_MODE_0, i_tgt, GRP3, LANE_00, 0x1));
-    FAPI_TRY(io::rmw(EDIP_RX_PG_SPARE_MODE_1, i_tgt, GRP3, LANE_00, 0x0));
-    FAPI_TRY(io::rmw(EDIP_RX_PG_SPARE_MODE_2, i_tgt, GRP3, LANE_00, 0x1));
-
-    // Since we fixing the common mode at the summer node, we need to rerun:
-    // - H1 To A Cal
-    // - H1 Cal
-    FAPI_TRY(io::rmw(EDIP_RX_EO_ENABLE_DAC_H1_TO_A_CAL, i_tgt, GRP3, LANE_00, 0x1));
-    FAPI_TRY(io::rmw(EDIP_RX_EO_ENABLE_DAC_H1_CAL,      i_tgt, GRP3, LANE_00, 0x1));
-
-    // As we are modifying the Common Mode, we need to disable the CM Fine Calibration,
-    //   otherwise this calibration will overwrite any fixes we apply.
-    FAPI_TRY(io::rmw(EDIP_RX_RC_ENABLE_CM_FINE_CAL, i_tgt, GRP3, LANE_00, 0x0));
-
-
-    for(uint8_t l_lane = 0; l_lane < XBUS_LANES; ++l_lane)
-    {
-        FAPI_TRY(io::read(EDIP_RX_A_INTEG_COARSE_GAIN, i_tgt, GRP3, l_lane, l_data));
-
-        l_cmcrs = io::get(EDIP_RX_A_INTEG_COARSE_GAIN, l_data);
-        l_cmcrs = (l_cmcrs * 5) / 10;
-        io::set(EDIP_RX_A_INTEG_COARSE_GAIN, l_cmcrs, l_data);
-
-        FAPI_TRY(io::write(EDIP_RX_A_INTEG_COARSE_GAIN, i_tgt, GRP3, l_lane, l_data));
-    }
-
-fapi_try_exit:
-    FAPI_IMP("p9_dmi_override_cm: I/O EDI+ Xbus Exiting");
-    return fapi2::current_err;
-}
-
-/**
  * @brief Start Cleanup Pll
  * @param[in] i_tgt FAPI2 Target
  * @retval ReturnCode
@@ -890,9 +842,6 @@ fapi2::ReturnCode rx_dccal_poll_grp(const DMI_TGT i_tgt)
     // Restore the invalid bits, Wiretest will modify these as training is run.
     FAPI_TRY(set_lanes_invalid(i_tgt, 1), "Error Setting Lane Invalid to 1");
 
-    // Run DMI Common Mode Workaround
-    FAPI_TRY( p9_dmi_override_cm( i_tgt ), "Error Running P9 Xbus Common Mode Workaround" );
-
     FAPI_DBG("I/O EDI+ Dmi Rx Dccal Complete");
 
 
diff --git a/src/import/chips/p9/procedures/hwp/io/p9_io_regs.H b/src/import/chips/p9/procedures/hwp/io/p9_io_regs.H
index 11fec59b9..f98504953 100644
--- a/src/import/chips/p9/procedures/hwp/io/p9_io_regs.H
+++ b/src/import/chips/p9/procedures/hwp/io/p9_io_regs.H
@@ -193,13 +193,6 @@
 #define EDIP_RX_BER_TIMEOUT                                0x800888000000003f, 56,  4 // rx_ber_timeout, used for when making bit error measurements with a servo op (see workbook table 4.10 for timer settings)
 #define EDIP_RX_CTL_MODE16_EO_PG                           0x800888000000003f, 48, 16 // register -- description
 #define EDIP_CHAN_FAIL_MASK                                0x0000000000000020, 15,  8 // scom mode reg spares.
-#define EDIP_RX_PG_SPARE_MODE_0                            0x800800000000003f, 48,  1 // per-group spare mode latch.
-#define EDIP_RX_PG_SPARE_MODE_1                            0x800800000000003f, 49,  1 // per-group spare mode latch.
-#define EDIP_RX_PG_SPARE_MODE_2                            0x800800000000003f, 50,  1 // per-group spare mode latch.
-#define EDIP_RX_RC_ENABLE_CM_FINE_CAL                      0x8008b8000000003f, 56,  1 // rx recalibration    common mode fine calibration enable
-#define EDIP_RX_EO_ENABLE_DAC_H1_CAL                       0x8008b0000000003f, 50,  1 // rx eye optimization h! dac calibration to reference
-#define EDIP_RX_EO_ENABLE_DAC_H1_TO_A_CAL                  0x8008b0000000003f, 61,  1 // rx eye optimization h! dac to amplitude dac cross-calibration
-#define EDIP_RX_A_INTEG_COARSE_GAIN                        0x800028000000003f, 48,  4 // this is integrator coarse gain control used in making common mode adjustments.
 
 
 #define EDI_RX_WTM_STATE                                   0x800950000000003f, 48,  5 // main wiretest state machine current state (rjr)): \r\n\tx00: idle \r\n\tx01: drv data  wt \r\n\tx02: drv clock wt \r\n\tx03: drv data  0 \r\n\tx04: drv clock 0 \r\n\tx05: rx wt \r\n\tx06: wait all ones \r\n\tx07: reset pll \r\n\tx08: wait pll \r\n\tx09: drive clock \r\n\tx0a: drive data 1 \r\n\tx0b: wait all zeroes \r\n\tx0c: drive data 0 \r\n\tx0d: done \r\n\tx0e: unused \r\n\tx0f: unused \r\n\tx10: wait prev done \r\n\tx11: drv prev done \r\n\tx12: drv all done \r\n\tx13: wait all done \r\n\tx14: init tx fifo \r\n\tx15: unused \r\n\tx16: unused \r\n\tx17: unused \r\n\tx18: set c & d dr strength \r\n\tx19: set data only dr strength \r\n\tx1a: clock fail \r\n\tx1b: all bad lanes \r\n\tx1c: wt timeout fail \r\n\tx1d: pll/dll fail \r\n\tx1e: all ones fail \r\n\tx1f: all zeroes fail \r\n\trjr
@@ -2503,6 +2496,7 @@
 #define EDIP_RX_A_OFFSET_O0                                0x800020000000003f, 48,  7 // this is the vertical offset of the odd low threshold sampling latch.
 #define EDIP_RX_A_OFFSET_O1                                0x800020000000003f, 56,  7 // this is the vertical offset of the odd high threshold sampling latch.
 #define EDIP_RX_DAC_CNTL4_EO_PL                            0x800020000000003f, 48, 16 // register -- description
+#define EDIP_RX_A_INTEG_COARSE_GAIN                        0x800028000000003f, 48,  4 // this is integrator coarse gain control used in making common mode adjustments.
 #define EDIP_RX_A_EVEN_INTEG_FINE_GAIN                     0x800028000000003f, 52,  5 // this is integrator gain control used in making common mode adjustments.
 #define EDIP_RX_A_ODD_INTEG_FINE_GAIN                      0x800028000000003f, 57,  5 // this is integrator gain control used in making common mode adjustments.
 #define EDIP_RX_DAC_CNTL5_EO_PL                            0x800028000000003f, 48, 16 // register -- description
@@ -2709,6 +2703,9 @@
 #define EDIP_RX_A_PATH_OFF_EVEN                            0x800398000000003f, 48,  6 // eye opt a bank even path offset
 #define EDIP_RX_A_PATH_OFF_ODD                             0x800398000000003f, 54,  6 // eye opt a bank odd  path offset
 #define EDIP_RX_WORK_STAT3_EO_PL                           0x800398000000003f, 48, 16 // register -- description
+#define EDIP_RX_PG_SPARE_MODE_0                            0x800800000000003f, 48,  1 // per-group spare mode latch.
+#define EDIP_RX_PG_SPARE_MODE_1                            0x800800000000003f, 49,  1 // per-group spare mode latch.
+#define EDIP_RX_PG_SPARE_MODE_2                            0x800800000000003f, 50,  1 // per-group spare mode latch.
 #define EDIP_RX_PG_SPARE_MODE_3                            0x800800000000003f, 51,  1 // per-group spare mode latch.
 #define EDIP_RX_PG_SPARE_MODE_4                            0x800800000000003f, 52,  1 // chicken switch for hw219893.  fix is to prevent the rx_sls_hndshk_state sm and the rx_dyn_recal_hndshk_state sm from ever being allowed to run at the same time.  setting the cs turns this feature off.
 #define EDIP_RX_SPARE_MODE_PG                              0x800800000000003f, 48, 16 // register -- description
@@ -2806,6 +2803,7 @@
 #define EDIP_RX_EO_STEP_CNTL_EDI_ALIAS                     0x8008b0000000003f, 48, 16 // rx eye optimization step control edi alias
 #define EDIP_RX_EO_ENABLE_INTEG_LATCH_OFFSET_CAL           0x8008b0000000003f, 48,  1 // rx eye optimization latch offset adjustment enable with integrator-based disable
 #define EDIP_RX_EO_ENABLE_CTLE_COARSE_CAL                  0x8008b0000000003f, 49,  1 // rx eye optimization coarse ctle/peakin enable
+#define EDIP_RX_EO_ENABLE_DAC_H1_CAL                       0x8008b0000000003f, 50,  1 // rx eye optimization h! dac calibration to reference
 #define EDIP_RX_EO_ENABLE_VGA_CAL                          0x8008b0000000003f, 51,  1 // rx eye optimization vga gainand offset adjust enable
 #define EDIP_RX_EO_ENABLE_DFE_H1_CAL                       0x8008b0000000003f, 52,  1 // rx eye optimization dfe h1  adjust enable
 #define EDIP_RX_EO_ENABLE_H1AP_TWEAK                       0x8008b0000000003f, 53,  1 // rx eye optimization h1/an pr adjust enable
@@ -2816,6 +2814,7 @@
 #define EDIP_RX_EO_ENABLE_RESULT_CHECK                     0x8008b0000000003f, 58,  1 // rx eye optimization final results check enable
 #define EDIP_RX_EO_ENABLE_CTLE_EDGE_TRACK_ONLY             0x8008b0000000003f, 59,  1 // rx eye optimization ctle/peakin enable with edge tracking only
 #define EDIP_RX_EO_ENABLE_DFE_H2_H12_CAL                   0x8008b0000000003f, 60,  1 // rx eye optimization dfe h2 to h12 calibration enable
+#define EDIP_RX_EO_ENABLE_DAC_H1_TO_A_CAL                  0x8008b0000000003f, 61,  1 // rx eye optimization h! dac to amplitude dac cross-calibration
 #define EDIP_RX_EO_ENABLE_FINAL_L2U_ADJ                    0x8008b0000000003f, 62,  1 // rx eye optimization final rx fifo load-to-unload delay adjustment enable
 #define EDIP_RX_EO_ENABLE_DONE_SIGNALING                   0x8008b0000000003f, 63,  1 // rx eye optimization eye opt done signaling enable
 #define EDIP_RX_CTL_MODE21_EO_PG                           0x8008b0000000003f, 48, 16 // register -- description
@@ -2828,6 +2827,7 @@
 #define EDIP_RX_RC_ENABLE_H1AP_TWEAK                       0x8008b8000000003f, 53,  1 // rx recalibration    h1/an pr adjust enable
 #define EDIP_RX_RC_ENABLE_DDC                              0x8008b8000000003f, 54,  1 // rx recalibration    dynamic data centering enable
 #define EDIP_RX_RC_ENABLE_CM_COARSE_CAL                    0x8008b8000000003f, 55,  1 // rx recalibration    common mode coarse calibration enable
+#define EDIP_RX_RC_ENABLE_CM_FINE_CAL                      0x8008b8000000003f, 56,  1 // rx recalibration    common mode fine calibration enable
 #define EDIP_RX_RC_ENABLE_BER_TEST                         0x8008b8000000003f, 57,  1 // rx recalibration    unsupported, leave at 0. bit error rate test enable
 #define EDIP_RX_RC_ENABLE_RESULT_CHECK                     0x8008b8000000003f, 58,  1 // rx recalibration    unsupported, leave at 0. final results check enable
 #define EDIP_RX_RC_ENABLE_CTLE_EDGE_TRACK_ONLY             0x8008b8000000003f, 59,  1 // rx recalibration    ctle/peaking enable with edge tracking only
diff --git a/src/import/chips/p9/procedures/hwp/io/p9_io_xbus_dccal.C b/src/import/chips/p9/procedures/hwp/io/p9_io_xbus_dccal.C
index 9fe5af400..8e421dab6 100644
--- a/src/import/chips/p9/procedures/hwp/io/p9_io_xbus_dccal.C
+++ b/src/import/chips/p9/procedures/hwp/io/p9_io_xbus_dccal.C
@@ -730,43 +730,6 @@ fapi_try_exit:
     return fapi2::current_err;
 }
 
-
-/**
- * @brief Xbus Common Mode Workaround
- * @param[in] i_tgt FAPI2 Target
- * @param[in] i_grp Clock Group
- * @retval ReturnCode
- */
-fapi2::ReturnCode p9x_cm_workaround( const XBUS_TGT i_tgt, const uint8_t i_grp )
-{
-    FAPI_IMP( "p9x_cm_workaround: I/O EDI+ Xbus Entering" );
-    const uint8_t CMDAC      = 5; // Initialize with a CMDAC = 2
-    const uint8_t XBUS_LANES = 17;
-    const uint8_t LN0        = 0;
-    uint32_t      l_cm_crs   = 0;
-    uint64_t      l_data     = 0;
-
-    FAPI_TRY( io::rmw( EDIP_RX_PG_SPARE_MODE_0, i_tgt, i_grp, LN0, ((CMDAC >> 2) & 0x1)));
-    FAPI_TRY( io::rmw( EDIP_RX_PG_SPARE_MODE_1, i_tgt, i_grp, LN0, ((CMDAC >> 1) & 0x1)));
-    FAPI_TRY( io::rmw( EDIP_RX_PG_SPARE_MODE_2, i_tgt, i_grp, LN0, ((CMDAC >> 0) & 0x1)));
-    FAPI_TRY( io::rmw( EDIP_RX_RC_ENABLE_CM_FINE_CAL, i_tgt, i_grp, LN0, 0));
-    FAPI_TRY( io::rmw( EDIP_RX_EO_ENABLE_DAC_H1_TO_A_CAL, i_tgt, i_grp, LN0, 1));
-    FAPI_TRY( io::rmw( EDIP_RX_EO_ENABLE_DAC_H1_CAL, i_tgt, i_grp, LN0, 1));
-
-    for( uint8_t l_lane = 0; l_lane < XBUS_LANES; ++l_lane )
-    {
-        FAPI_TRY( io::read( EDIP_RX_A_INTEG_COARSE_GAIN, i_tgt, i_grp, l_lane, l_data ));
-        l_cm_crs = io::get( EDIP_RX_A_INTEG_COARSE_GAIN, l_data );
-        l_cm_crs = ( l_cm_crs * 5 ) / 10;
-        FAPI_TRY( io::rmw( EDIP_RX_A_INTEG_COARSE_GAIN, i_tgt, i_grp, l_lane, l_cm_crs));
-    }
-
-fapi_try_exit:
-    FAPI_IMP( "p9x_cm_workaround: I/O EDI+ Xbus Exiting" );
-    return fapi2::current_err;
-}
-
-
 /**
  * @brief Rx Dc Calibration
  * @param[in] i_tgt FAPI2 Target
@@ -879,9 +842,6 @@ fapi2::ReturnCode rx_dccal_poll_grp( const XBUS_TGT i_tgt, const uint8_t  i_grp
     // Restore the invalid bits, Wiretest will modify these as training is run.
     FAPI_TRY( set_lanes_invalid( i_tgt, i_grp, 1 ), "Error Setting Lane Invalid to 1" );
 
-    // FW685728 : Data Compression Workaround
-    FAPI_TRY( p9x_cm_workaround( i_tgt, i_grp ), "p9x_cm_workound call failed" );
-
     FAPI_DBG( "I/O EDI+ Xbus Rx Dccal Complete on Group(%d)", i_grp );