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| author | Dean Sanner <dsanner@us.ibm.com> | 2017-01-13 20:48:00 -0600 |
|---|---|---|
| committer | William G. Hoffa <wghoffa@us.ibm.com> | 2017-01-17 13:37:25 -0500 |
| commit | ec6e46d87faca9cada3a365d2e0c8a125875ad90 (patch) | |
| tree | 6247e41f6474e48b1cb0d09a90eef1b9f44a6959 /src/import/chips/p9/procedures/hwp/pm/p9_update_ec_eq_state.C | |
| parent | ccaed40ee1fe7cff8c5879adb6eb788f44ef577c (diff) | |
| download | talos-hostboot-ec6e46d87faca9cada3a365d2e0c8a125875ad90.tar.gz talos-hostboot-ec6e46d87faca9cada3a365d2e0c8a125875ad90.zip | |
Set the quad stop state on non master chips
Change-Id: Ide1c009e65892b50822259e99028a3db73d73a2d
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/34886
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Gregory S. Still <stillgs@us.ibm.com>
Reviewed-by: CHRISTOPHER M. RIEDL <cmriedl@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/34890
Reviewed-by: Hostboot Team <hostboot@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: William G. Hoffa <wghoffa@us.ibm.com>
Diffstat (limited to 'src/import/chips/p9/procedures/hwp/pm/p9_update_ec_eq_state.C')
| -rw-r--r-- | src/import/chips/p9/procedures/hwp/pm/p9_update_ec_eq_state.C | 18 |
1 files changed, 17 insertions, 1 deletions
diff --git a/src/import/chips/p9/procedures/hwp/pm/p9_update_ec_eq_state.C b/src/import/chips/p9/procedures/hwp/pm/p9_update_ec_eq_state.C index f4cdbbe7a..c680127b7 100644 --- a/src/import/chips/p9/procedures/hwp/pm/p9_update_ec_eq_state.C +++ b/src/import/chips/p9/procedures/hwp/pm/p9_update_ec_eq_state.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* Contributors Listed Below - COPYRIGHT 2015,2017 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -133,6 +133,8 @@ static const uint8_t BROADCAST_GROUP = 7; fapi2::ReturnCode p9_update_ec_eq_state( const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target) { + fapi2::buffer<uint64_t> l_data64 = 0; + FAPI_IMP("> p9_update_ec_eq_state"); FAPI_TRY(update_ec_config(i_target), @@ -141,6 +143,20 @@ fapi2::ReturnCode p9_update_ec_eq_state( FAPI_TRY(update_eq_config(i_target), "Error update_cache_config detected"); + + //If this is NOT the master processor then need to set + //the default value the OCC Quad Status Status Register + //As the SBE doesn't do this on the slave chips + FAPI_TRY(fapi2::getScom(i_target, PU_OCB_OCI_QSSR_SCOM, l_data64)); + + if(l_data64() == 0x0) + { + l_data64.setBit<0, 12>(); // L2 Stopped + l_data64.setBit<14, 6>(); // Quad Stopped + FAPI_TRY(fapi2::putScom(i_target, PU_OCB_OCI_QSSR_SCOM2, l_data64)); + } + + fapi_try_exit: FAPI_INF("< p9_update_ec_eq_state"); |
