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| author | Rahul Batra <rbatra@us.ibm.com> | 2017-07-18 00:24:21 -0500 |
|---|---|---|
| committer | Daniel M. Crowell <dcrowell@us.ibm.com> | 2017-08-04 10:44:38 -0400 |
| commit | 0213ac4d1adbdac43a057cffd4df541c861eedbc (patch) | |
| tree | 485b6358223f19c504bbc2991cd42aef9a288d6b /src/import/chips/p9/procedures/hwp/pm/p9_pstate_parameter_block.C | |
| parent | 25d477f208be87dd23e89e0289695e81fa68a854 (diff) | |
| download | talos-hostboot-0213ac4d1adbdac43a057cffd4df541c861eedbc.tar.gz talos-hostboot-0213ac4d1adbdac43a057cffd4df541c861eedbc.zip | |
PM: DPLL0 value off by 1 in GPPB and LPPB fix
Change-Id: I5c5a675e19c97f4471e4d169b6e16449e38674fe
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/43247
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: RANGANATHPRASAD G. BRAHMASAMUDRA <prasadbgr@in.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Michael S. Floyd <mfloyd@us.ibm.com>
Reviewed-by: CHRISTOPHER M. RIEDL <cmriedl@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/43249
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Diffstat (limited to 'src/import/chips/p9/procedures/hwp/pm/p9_pstate_parameter_block.C')
| -rw-r--r-- | src/import/chips/p9/procedures/hwp/pm/p9_pstate_parameter_block.C | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/src/import/chips/p9/procedures/hwp/pm/p9_pstate_parameter_block.C b/src/import/chips/p9/procedures/hwp/pm/p9_pstate_parameter_block.C index ce21aa1c9..76fb2d26f 100644 --- a/src/import/chips/p9/procedures/hwp/pm/p9_pstate_parameter_block.C +++ b/src/import/chips/p9/procedures/hwp/pm/p9_pstate_parameter_block.C @@ -486,8 +486,7 @@ p9_pstate_parameter_block( const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_ p9_pstate_compute_PsV_slopes(l_operating_points, &l_globalppb); //Remote this RTC: 174743 p9_pstate_compute_PStateV_slope(l_operating_points, &l_globalppb); - l_globalppb.dpll_pstate0_value = revle32((revle32(l_globalppb.reference_frequency_khz) + revle32( - l_globalppb.frequency_step_khz) - 1) / revle32( + l_globalppb.dpll_pstate0_value = revle32(revle32(l_globalppb.reference_frequency_khz) / revle32( l_globalppb.frequency_step_khz)); FAPI_INF("l_globalppb.dpll_pstate0_value %X", revle32(l_globalppb.dpll_pstate0_value)); @@ -510,8 +509,9 @@ p9_pstate_parameter_block( const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_ l_localppb.vdm = l_lp_vdmpb; - l_localppb.dpll_pstate0_value = revle32((revle32(l_localppb.operating_points[ULTRA].frequency_mhz) * 1000 / revle32( - l_globalppb.frequency_step_khz))); + l_localppb.dpll_pstate0_value = revle32(revle32(l_globalppb.reference_frequency_khz) / revle32( + l_globalppb.frequency_step_khz)); + FAPI_INF("l_localppb.dpll_pstate0_value %X", revle32(l_localppb.dpll_pstate0_value)); |
