Chip address extension workaround for HW423589 (option2), part1

chip_ec_attributes.xml
nest_attributes.xml
p9_sbe_attributes.xml
  add ATTR_CHIP_EC_FEATURE_EXTENDED_ADDRESSING_MODE, defines
    set of chips which physically support the feature
  add ATTR_CHIP_EC_FEATURE_HW423589_OPTION2, defines set of chips
    which need extended address workaround for MCD issue (applied only
    to Nimbus EC 21)
  add ATTR_MAX_INTERLEAVE_GROUP_SIZE, to restrict maximum size of
    memory groups formed.  Written by p9_mss_eff_grouping.  For
    HW423589_OPTION2, this will default to 512GB
  add ATTR_FABRIC_ADDR_EXTENSION_[GROUP|CHIP]_ID, to hold
    extended address configuration.  Written by p9_sbe_fabricinit (SBE)
    and p9_mss_eff_grouping (HB).  For HW423589_OPTION2, this will
    default to 0b0000_111, consuming all chip ID bits for extended
    addressing.

p9_fbc_utils.C
p9_fbc_utils.H
  extend p9_fbc_utils_get_chip_base_address to support address
  extension, now outputs set of ranges in each msel based on
  ATTR_FABRIC_ADDR_EXTENSION[GROUP|CHIP]_ID

  maintain original function for PPE platform which requires
  knowledge of non-aliased base addresses only, for code size

p9_mss_eff_grouping.C
p9_mss_eff_grouping_errors.xml
  set ATTR_FABRIC_ADDR_EXTENSION[GROUP|CHIP]_ID for HB platform
  restrict size of groups formed for HW423589_OPTION2

p9_sbe_fabricinit.C
  set ATTR_FABRIC_ADDR_EXTENSION[GROUP|CHIP]_ID for SBE platform
  configure FBC/NMMU extended addressing registers

p9_setup_bars.C
p9_setup_bars_defs.H
p9_setup_bars_errors.xml
  add general purpose support for extended address mode
  for HW423589_OPTION2, configure static MCD setup

p9_hcode_image_defines.H
p9_hcode_image_build.C
  customize SGPE image with address extension configuration to apply

p9.cxa.scom.initfile
p9.int.scom.initfile
p9.l2.scom.initfile
p9.l3.scom.initfile
p9.ncu.scom.initfile
p9.nx.scom.initfile
p9.trace.scan.initfile
p9.vas.scom.initfile
p9_hcd_cache_scominit.C
p9_hcd_cache_scominit.c
p9_pcie_config.C
  set unit address extension configuration on supported chips

p9_rng_init_phase2.C
p9_sbe_scominit.C
p9c_set_inband_addr.C
p9_sbe_load_bootloader.C
p9_sbe_mcs_setup.C
  adapt to alterations in p9_fbc_utils_get_chip_base_address

Change-Id: I614d566c073f1169f04f647057e6e85889f1c237
CQ: HW423589
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/48576
Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Gregory S. Still <stillgs@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/48893
Reviewed-by: Hostboot Team <hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>

1 files changed, 41 insertions, 3 deletions

diff --git a/src/import/chips/p9/procedures/hwp/pm/p9_hcode_image_build.C b/src/import/chips/p9/procedures/hwp/pm/p9_hcode_image_build.C
index 717cb5f22..75cd9dcb0 100644
--- a/src/import/chips/p9/procedures/hwp/pm/p9_hcode_image_build.C
+++ b/src/import/chips/p9/procedures/hwp/pm/p9_hcode_image_build.C
@@ -3451,11 +3451,17 @@ fapi2::ReturnCode setFabricIds( Homerlayout_t* i_pChipHomer, CONST_FAPI2_PROC& i
 {
 
     FAPI_INF(">> setFabricIds");
+    const fapi2::Target<fapi2::TARGET_TYPE_SYSTEM> FAPI_SYSTEM;
     uint32_t l_system_id;
     uint8_t  l_group_id;
     uint8_t  l_chip_id;
+    uint8_t  l_addr_extension_group_id;
+    uint8_t  l_addr_extension_chip_id;
     fapi2::buffer<uint16_t> l_location_id = 0;
+    fapi2::buffer<uint16_t> l_addr_extension = 0;
+    fapi2::ATTR_CHIP_EC_FEATURE_EXTENDED_ADDRESSING_MODE_Type l_extended_addressing_mode;
     uint16_t l_locationVal = 0;
+    uint16_t l_addr_extension_val = 0;
 
     cmeHeader_t* pCmeHdr = (cmeHeader_t*) & i_pChipHomer->cpmrRegion.cmeSramRegion[CME_INT_VECTOR_SIZE];
     sgpeHeader_t* pSgpeHdr = (sgpeHeader_t*)& i_pChipHomer->qpmrRegion.sgpeRegion.sgpeSramImage[SGPE_INT_VECTOR_SIZE];
@@ -3502,6 +3508,39 @@ fapi2::ReturnCode setFabricIds( Homerlayout_t* i_pChipHomer, CONST_FAPI2_PROC& i
     // Populate the SGPE Header
     pSgpeHdr->g_sgpe_location_id = SWIZZLE_2_BYTE(l_locationVal);
 
+    // configure extended addressing facility
+    // only place non zero value in SGPE header if supported by chip type
+    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_EC_FEATURE_EXTENDED_ADDRESSING_MODE,
+                           i_procTgt,
+                           l_extended_addressing_mode),
+             "Error from FAPI_ATTR_GET (ATTR_CHIP_EC_FEATURE_EXTENDED_ADDRESSING_MODE)");
+
+    if (l_extended_addressing_mode)
+    {
+        FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_FABRIC_ADDR_EXTENSION_GROUP_ID,
+                               FAPI_SYSTEM,
+                               l_addr_extension_group_id),
+                 "Error from FAPI_ATTR_GET for attribute ATTR_FABRIC_ADDR_EXTENSION_GROUP_ID");
+
+        FAPI_DBG("Fabric Address Extension Group ID  :   0x%01X", l_addr_extension_group_id);
+
+        FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_FABRIC_ADDR_EXTENSION_CHIP_ID,
+                               FAPI_SYSTEM,
+                               l_addr_extension_chip_id),
+                 "Error from FAPI_ATTR_GET for attribute ATTR_FABRIC_ADDR_EXTENSION_CHIP_ID");
+
+        FAPI_DBG("Fabric Address Extension Chip ID   :   0x%01X", l_addr_extension_chip_id);
+
+        l_addr_extension.insert<0, 4, 8-4, uint8_t>(l_addr_extension_group_id);
+        l_addr_extension.insert<4, 3, 8-3, uint8_t>(l_addr_extension_chip_id);
+    }
+
+    FAPI_DBG("Address Extension ID   :   0x%04X", l_addr_extension);
+    l_addr_extension.extract<0, 16>(l_addr_extension_val);
+
+    // Populate the SGPE Header
+    pSgpeHdr->g_sgpe_addr_extension = SWIZZLE_2_BYTE(l_addr_extension_val);
+
 fapi_try_exit:
     FAPI_INF("<< setFabricIds");
     return fapi2::current_err;
@@ -3523,9 +3562,8 @@ fapi2::ReturnCode populateNcuRngBarScomReg( void* i_pChipHomer, CONST_FAPI2_PROC
     uint8_t  attrVal = 0;
     uint64_t nxRangeBarAddrOffset = 0;
     uint64_t regNcuRngBarData   = 0;
-    uint64_t baseAddressNm0     = 0;
-    uint64_t baseAddressNm1     = 0;
-    uint64_t baseAddressMirror  = 0;
+    std::vector<uint64_t> baseAddressNm0, baseAddressNm1;
+    std::vector<uint64_t> baseAddressMirror;
     uint32_t ncuBarRegisterAddr = 0;
     const fapi2::Target<fapi2::TARGET_TYPE_SYSTEM> FAPI_SYSTEM;