Additional risk level support - (step 2) Updating the image w/RL2

This commit changes the images' .rings section by adding the TOR
RL2 variant slot to the runtime Quad chiplets, EQ and EC.

Specifically, we have changed the definition of the ATTR_RISK_LEVEL
attribute to now have three risk levels, RL0 (prev FALSE), RL1
(prev TRUE) and RL2 (new). To accomodate RL2, a new "override"
txt file has been created, ./attribute_ovd/runtime_risk2.txt and
changes to many other files using the ATTR_RISK_LEVEL attrib have
been updated as well.

Lastly, and to allow for the inclusion of RL2 rings in the HW
image, the TOR_VERSION has been updated to version 6 which will
allow for RL2 support in the ring ID metadata files.

p9_setup_sbe_config is updated to write the RISK_LEVEL value into
scratch 3 bits 28:31, and deprecate the existing mailbox.

RISK_LEVEL processing has been removed from p9_sbe_attr_setup. It's
only function is to seed mailboxes which are empty via the
attribute state present in the SEEPROM.  Since RISK_LEVEL is zero
at image build time, and explicitly cleared as a result of every
customization, there's logically no need to process the RISK_LEVEL
here.

PPE changes to accomodate the new RISK_LEVEL mailbox
location need to be implemented in the PLAT code: src/hwpf/target.C

Key_Cronus_Test=XIP_REGRESS

HW-ImageBuild-Preqeq=52659
- 52659 must be fully merged in Cronus and HB before this commit
  (53292) can be merged. This is to avoid a Coreq situation.

CQ: SW416424
cmvc-prereq: 1046058
cmvc-prereq: 1043606
cmvc-prereq: 1045920
Change-Id: Ia0471219916602cc0041a2c55a1070013f66a7d9
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/53292
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Cronus HW CI <cronushw-ci+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Richard J. Knight <rjknight@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/53321
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>

1 files changed, 8 insertions, 12 deletions

diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_setup_sbe_config.C b/src/import/chips/p9/procedures/hwp/perv/p9_setup_sbe_config.C
index f0b07d763..a6144985b 100644
--- a/src/import/chips/p9/procedures/hwp/perv/p9_setup_sbe_config.C
+++ b/src/import/chips/p9/procedures/hwp/perv/p9_setup_sbe_config.C
@@ -72,6 +72,8 @@ enum P9_SETUP_SBE_CONFIG_Private_Constants
     // Scratch_reg_3
     ATTR_BOOT_FLAGS_STARTBIT           = 0,
     ATTR_BOOT_FLAGS_LENGTH             = 32,
+    ATTR_RISK_LEVEL_STARTBIT           = 28,
+    ATTR_RISK_LEVEL_LENGTH             = 4,
 
     // Scratch_reg_4
     ATTR_BOOT_FREQ_MULT_STARTBIT       = 0,
@@ -90,7 +92,7 @@ enum P9_SETUP_SBE_CONFIG_Private_Constants
     ATTR_PLL_MUX_LENGTH                = 20,
     ATTR_CC_IPL_BIT                    = 0,
     ATTR_INIT_ALL_CORES_BIT            = 1,
-    ATTR_RISK_LEVEL_BIT                = 2,
+    ATTR_RISK_LEVEL_BIT_DEPRECATED     = 2,
     ATTR_DISABLE_HBBL_VECTORS_BIT      = 3,
     ATTR_MC_SYNC_MODE_BIT              = 4,
     ATTR_SLOW_PCI_REF_CLOCK_BIT        = 5,
@@ -297,6 +299,7 @@ fapi2::ReturnCode p9_setup_sbe_config(const
     //set_scratch3_reg
     {
         FAPI_DBG("Reading Scratch_reg3");
+        uint8_t l_risk_level;
 
         if ( l_accessViaScom )
         {
@@ -313,8 +316,10 @@ fapi2::ReturnCode p9_setup_sbe_config(const
 
         FAPI_DBG("Reading the BOOT_FLAGS");
         FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_BOOT_FLAGS, FAPI_SYSTEM, l_read_5));
+        FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_RISK_LEVEL, FAPI_SYSTEM, l_risk_level));
 
         l_read_scratch_reg.insertFromRight< ATTR_BOOT_FLAGS_STARTBIT, ATTR_BOOT_FLAGS_LENGTH >(l_read_5);
+        l_read_scratch_reg.insertFromRight< ATTR_RISK_LEVEL_STARTBIT, ATTR_RISK_LEVEL_LENGTH >(l_risk_level);
 
         FAPI_DBG("Setting up value of Scratch_reg3");
 
@@ -414,7 +419,6 @@ fapi2::ReturnCode p9_setup_sbe_config(const
     {
         uint8_t l_system_ipl_phase;
         uint8_t l_force_all_cores;
-        uint8_t l_risk_level;
         uint8_t l_disable_hbbl_vectors;
         uint32_t l_pll_mux;
         uint8_t l_mc_sync_mode;
@@ -438,7 +442,6 @@ fapi2::ReturnCode p9_setup_sbe_config(const
         FAPI_DBG("Reading control flag attributes");
         FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_SYSTEM_IPL_PHASE, FAPI_SYSTEM, l_system_ipl_phase));
         FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_SYS_FORCE_ALL_CORES, FAPI_SYSTEM, l_force_all_cores));
-        FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_RISK_LEVEL, FAPI_SYSTEM, l_risk_level));
         FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_DISABLE_HBBL_VECTORS, FAPI_SYSTEM, l_disable_hbbl_vectors));
         FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_MC_SYNC_MODE, i_target_chip, l_mc_sync_mode));
         FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_DD1_SLOW_PCI_REF_CLOCK, FAPI_SYSTEM, l_slow_pci_ref_clock));
@@ -463,15 +466,8 @@ fapi2::ReturnCode p9_setup_sbe_config(const
             l_read_scratch_reg.clearBit<ATTR_INIT_ALL_CORES_BIT>();
         }
 
-        // set risk level flag
-        if (l_risk_level == fapi2::ENUM_ATTR_RISK_LEVEL_TRUE)
-        {
-            l_read_scratch_reg.setBit<ATTR_RISK_LEVEL_BIT>();
-        }
-        else
-        {
-            l_read_scratch_reg.clearBit<ATTR_RISK_LEVEL_BIT>();
-        }
+        // risk level flag is deprecated here, moved to scratch3
+        l_read_scratch_reg.clearBit<ATTR_RISK_LEVEL_BIT_DEPRECATED>();
 
         // set disable of HBBL exception vector flag
         if (l_disable_hbbl_vectors == fapi2::ENUM_ATTR_DISABLE_HBBL_VECTORS_TRUE)