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| author | Joe McGill <jmcgill@us.ibm.com> | 2017-06-12 13:01:28 -0500 |
|---|---|---|
| committer | Daniel M. Crowell <dcrowell@us.ibm.com> | 2017-06-19 13:49:42 -0400 |
| commit | 0483af65824cddb936e3450fa99234371929340b (patch) | |
| tree | d83b6386dfba90b8325a901fd2c5233cded9d33f /src/import/chips/p9/procedures/hwp/nest/p9_smp_link_layer.H | |
| parent | 12a64eb99ca387c7fa1112611d274d17c7537c30 (diff) | |
| download | talos-hostboot-0483af65824cddb936e3450fa99234371929340b.tar.gz talos-hostboot-0483af65824cddb936e3450fa99234371929340b.zip | |
L3 update -- p9_smp_link_layer
whitespace, line length updates
Change-Id: Iaa312ba533e99c4a018ca768c0c71edcfe7648ea
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/41698
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Thi N. Tran <thi@us.ibm.com>
Reviewed-by: Benjamin Gass <bgass@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/41701
Reviewed-by: Hostboot Team <hostboot@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Diffstat (limited to 'src/import/chips/p9/procedures/hwp/nest/p9_smp_link_layer.H')
| -rwxr-xr-x | src/import/chips/p9/procedures/hwp/nest/p9_smp_link_layer.H | 20 |
1 files changed, 9 insertions, 11 deletions
diff --git a/src/import/chips/p9/procedures/hwp/nest/p9_smp_link_layer.H b/src/import/chips/p9/procedures/hwp/nest/p9_smp_link_layer.H index 645393068..abf9fab06 100755 --- a/src/import/chips/p9/procedures/hwp/nest/p9_smp_link_layer.H +++ b/src/import/chips/p9/procedures/hwp/nest/p9_smp_link_layer.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* Contributors Listed Below - COPYRIGHT 2015,2017 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -42,20 +42,18 @@ // *HWP HWP Owner: Joe McGill <jmcgill@us.ibm.com> // *HWP FW Owner: Thi Tran <thi@us.ibm.com> // *HWP Team: Nest -// *HWP Level: 2 +// *HWP Level: 3 // *HWP Consumed by: HB,FSP // #ifndef _P9_SMP_LINK_LAYER_H_ #define _P9_SMP_LINK_LAYER_H_ - //------------------------------------------------------------------------------ // Includes //------------------------------------------------------------------------------ #include <fapi2.H> - //------------------------------------------------------------------------------ // Structure definitions //------------------------------------------------------------------------------ @@ -66,7 +64,6 @@ typedef fapi2::ReturnCode (*p9_smp_link_layer_FP_t) ( const bool, const bool); - //------------------------------------------------------------------------------ // Function prototypes //------------------------------------------------------------------------------ @@ -77,15 +74,16 @@ extern "C" /// /// @brief Train fabric DLL/TL layers /// -/// @param[in] i_target Reference to processor chip target -/// @param[in] i_train_electrical Train electrical links? -/// @param[in] i_train_optical Train optical links? +/// @param[in] i_target Reference to processor chip target +/// @param[in] i_train_electrical Train electrical links? +/// @param[in] i_train_optical Train optical links? /// /// @return fapi::ReturnCode. FAPI2_RC_SUCCESS if success, else error code. /// - fapi2::ReturnCode p9_smp_link_layer(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target, - const bool i_train_electrical, - const bool i_train_optical); + fapi2::ReturnCode p9_smp_link_layer( + const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target, + const bool i_train_electrical, + const bool i_train_optical); } // extern "C" |
