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| author | Ricardo Mata <ricmata@us.ibm.com> | 2018-04-06 17:57:24 -0500 |
|---|---|---|
| committer | Daniel M. Crowell <dcrowell@us.ibm.com> | 2018-04-11 20:25:37 -0400 |
| commit | 47d7bd9acefb0ab9dce479bdae61d80d742ebb03 (patch) | |
| tree | 98914c56dd6e6f40e02adf7a82a8ad425be94f6b /src/import/chips/p9/procedures/hwp/nest/p9_pcie_scominit.C | |
| parent | 744277d9a5c546340a011ea36a18471bd3cdcb85 (diff) | |
| download | talos-hostboot-47d7bd9acefb0ab9dce479bdae61d80d742ebb03.tar.gz talos-hostboot-47d7bd9acefb0ab9dce479bdae61d80d742ebb03.zip | |
Updated pcie_scominit and pcie_config to manage systems not using PEC STACK0.
Defect SW417485 used to track these changes.
Change-Id: I945ccd7726e2938fa07e8e3b118fc17e97111544
CQ: SW417485
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/56909
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: Thi N. Tran <thi@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/56910
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Diffstat (limited to 'src/import/chips/p9/procedures/hwp/nest/p9_pcie_scominit.C')
| -rw-r--r-- | src/import/chips/p9/procedures/hwp/nest/p9_pcie_scominit.C | 13 |
1 files changed, 12 insertions, 1 deletions
diff --git a/src/import/chips/p9/procedures/hwp/nest/p9_pcie_scominit.C b/src/import/chips/p9/procedures/hwp/nest/p9_pcie_scominit.C index 84b4573ff..ac00d7e61 100644 --- a/src/import/chips/p9/procedures/hwp/nest/p9_pcie_scominit.C +++ b/src/import/chips/p9/procedures/hwp/nest/p9_pcie_scominit.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2015,2017 */ +/* Contributors Listed Below - COPYRIGHT 2015,2018 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -64,6 +64,9 @@ const uint8_t PEC2_IOP_SWAP_START_BIT = 7; const uint8_t PEC0_IOP_IOVALID_ENABLE_START_BIT = 4; const uint8_t PEC1_IOP_IOVALID_ENABLE_START_BIT = 4; const uint8_t PEC2_IOP_IOVALID_ENABLE_START_BIT = 4; +const uint8_t PEC_IOP_IOVALID_ENABLE_STACK0_BIT = 4; +const uint8_t PEC_IOP_IOVALID_ENABLE_STACK1_BIT = 5; +const uint8_t PEC_IOP_IOVALID_ENABLE_STACK2_BIT = 6; const uint8_t PEC_IOP_REFCLOCK_ENABLE_START_BIT = 32; const uint8_t PEC_IOP_PMA_RESET_START_BIT = 29; const uint8_t PEC_IOP_PIPE_RESET_START_BIT = 28; @@ -257,6 +260,14 @@ fapi2::ReturnCode p9_pcie_scominit(const fapi2::Target<fapi2::TARGET_TYPE_PROC_C PEC1_IOP_IOVALID_ENABLE_START_BIT, PEC1_IOP_BIT_COUNT, PEC2_IOP_IOVALID_ENABLE_START_BIT, PEC2_IOP_BIT_COUNT)); FAPI_DBG("pec%i: %#lx", l_pec_id, l_buf()); + + // Set IOVALID for base PHB if PHB2, or PHB4, or PHB5 are set (SW417485) + if ((l_buf.getBit(PEC_IOP_IOVALID_ENABLE_STACK1_BIT)) || (l_buf.getBit(PEC_IOP_IOVALID_ENABLE_STACK2_BIT))) + { + l_buf.setBit<PEC_IOP_IOVALID_ENABLE_STACK0_BIT>(); + } + + FAPI_DBG("pec%i: %#lx", l_pec_id, l_buf()); FAPI_TRY(fapi2::putScom(l_pec_chiplets, PEC_CPLT_CONF1_OR, l_buf), "Error from putScom (0x%.16llX), PEC_CPLT_CONF1_OR"); |
