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| author | Joe McGill <jmcgill@us.ibm.com> | 2018-02-07 16:37:55 -0600 |
|---|---|---|
| committer | Daniel M. Crowell <dcrowell@us.ibm.com> | 2018-03-07 21:53:48 -0500 |
| commit | c0fce11639f72a479e3479a25362cf64337e51a1 (patch) | |
| tree | 7789826c7c6abea5673763833a21d7b3396fa687 /src/import/chips/p9/procedures/hwp/nest/p9_chiplet_fabric_scominit.mk | |
| parent | 2e0c75fb9d8c92e3145bc61a9dcc658399a13c9f (diff) | |
| download | talos-hostboot-c0fce11639f72a479e3479a25362cf64337e51a1.tar.gz talos-hostboot-c0fce11639f72a479e3479a25362cf64337e51a1.zip | |
enforce strict 512 GB per socket limit on Witherspoon memory map (part2)
first commit merged before HW testing was complete, and caused
issue with skiboot's detection of the MCD workaround mechanism
this update restores the chip address extension HW programming to 0x7,
(to avoid a coreq skiboot change) but should still restrict the allocation
to lie within the first 512 GB of address space on each socket
Change-Id: Ie844a609c16ffa1aa38091bae42145da9c7912a4
CQ: SW415901
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/53594
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Thi N. Tran <thi@us.ibm.com>
Reviewed-by: Jenny Huynh <jhuynh@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/53641
CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Diffstat (limited to 'src/import/chips/p9/procedures/hwp/nest/p9_chiplet_fabric_scominit.mk')
0 files changed, 0 insertions, 0 deletions
