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| author | Matthew Hickman <Matthew.Hickman@ibm.com> | 2017-11-29 17:14:19 -0600 |
|---|---|---|
| committer | Daniel M. Crowell <dcrowell@us.ibm.com> | 2018-03-07 21:50:55 -0500 |
| commit | f6b7234d960a9d00341fc3d7a7f179eeae79b317 (patch) | |
| tree | 04dd6c0586b00a1bbcf725ed9fc5288568127119 /src/import/chips/p9/procedures/hwp/memory | |
| parent | 1b11547e01a8e2be3bd08f52829686b787258d65 (diff) | |
| download | talos-hostboot-f6b7234d960a9d00341fc3d7a7f179eeae79b317.tar.gz talos-hostboot-f6b7234d960a9d00341fc3d7a7f179eeae79b317.zip | |
Fixed port fail SUE bug for DD2 modules
Change-Id: I8e1ab78c688684ceba1805277d1473c747248104
CQ: SW408973
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50166
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Louis Stermole <stermole@us.ibm.com>
Reviewed-by: ANDRE A. MARIN <aamarin@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: STEPHEN GLANCY <sglancy@us.ibm.com>
Dev-Ready: STEPHEN GLANCY <sglancy@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/54464
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Diffstat (limited to 'src/import/chips/p9/procedures/hwp/memory')
| -rw-r--r-- | src/import/chips/p9/procedures/hwp/memory/lib/fir/memdiags_fir.C | 8 |
1 files changed, 6 insertions, 2 deletions
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/fir/memdiags_fir.C b/src/import/chips/p9/procedures/hwp/memory/lib/fir/memdiags_fir.C index c15ea5220..7aa41f6d4 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/fir/memdiags_fir.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/fir/memdiags_fir.C @@ -94,14 +94,20 @@ fapi2::ReturnCode after_memdiags( const fapi2::Target<TARGET_TYPE_MCBIST>& i_tar .checkstop<MCA_FIR_MAINLINE_IAUE>() .recoverable_error<MCA_FIR_MAINLINE_IUE>(); + l_cal_fir_reg.recoverable_error<MCA_MBACALFIRQ_PORT_FAIL>(); + // If ATTR_CHIP_EC_FEATURE_HW414700 is enabled set checkstops auto l_chip_target = mss::find_target<fapi2::TARGET_TYPE_PROC_CHIP>(i_target); FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_CHIP_EC_FEATURE_HW414700, l_chip_target, l_checkstop_flag) ); + // If the system is running DD2 chips override some recoverable firs with checkstop + // Due to a known hardware defect with DD2 certain errors are not handled properly + // As a result, these firs are marked as checkstop for DD2 to avoid any mishandling if (l_checkstop_flag) { l_ecc64_fir_reg.checkstop<MCA_FIR_MAINLINE_UE>() .checkstop<MCA_FIR_MAINLINE_RCD>(); + l_cal_fir_reg.checkstop<MCA_MBACALFIRQ_PORT_FAIL>(); } // If MNFG FLAG Threshhold is enabled skip IUE unflagging @@ -112,8 +118,6 @@ fapi2::ReturnCode after_memdiags( const fapi2::Target<TARGET_TYPE_MCBIST>& i_tar l_ecc64_fir_reg.recoverable_error<MCA_FIR_MAINTENANCE_IUE>(); } - l_cal_fir_reg.recoverable_error<MCA_MBACALFIRQ_PORT_FAIL>(); - FAPI_TRY(l_ecc64_fir_reg.write(), "unable to write fir::reg %d", MCA_FIR); FAPI_TRY(l_cal_fir_reg.write(), "unable to write fir::reg %d", MCA_MBACALFIRQ); |
