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authorTsung Yeung <tyeung@us.ibm.com>2018-03-27 15:46:38 -0400
committerDaniel M. Crowell <dcrowell@us.ibm.com>2018-04-03 14:00:06 -0400
commit8e5461d3b3609aa630d65ea256a7f44b477a4771 (patch)
treeb1752a221ac4aa73bac23d909fd8131c4d897267 /src/import/chips/p9/procedures/hwp/memory
parentb77925c8ae2d8ac40455efa43a398da9238c4668 (diff)
downloadtalos-hostboot-8e5461d3b3609aa630d65ea256a7f44b477a4771.tar.gz
talos-hostboot-8e5461d3b3609aa630d65ea256a7f44b477a4771.zip
Includes NVDIMM in workaround for self-time refresh
Change-Id: I02b7be92d91aacd78188de6dc7b2c428701fa794 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/56333 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Louis Stermole <stermole@us.ibm.com> Reviewed-by: STEPHEN GLANCY <sglancy@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/56339 Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Diffstat (limited to 'src/import/chips/p9/procedures/hwp/memory')
-rw-r--r--src/import/chips/p9/procedures/hwp/memory/lib/workarounds/mca_workarounds.C32
1 files changed, 25 insertions, 7 deletions
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/workarounds/mca_workarounds.C b/src/import/chips/p9/procedures/hwp/memory/lib/workarounds/mca_workarounds.C
index 27202d57a..d6c6f3a42 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/workarounds/mca_workarounds.C
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/workarounds/mca_workarounds.C
@@ -5,7 +5,7 @@
/* */
/* OpenPOWER HostBoot Project */
/* */
-/* Contributors Listed Below - COPYRIGHT 2017 */
+/* Contributors Listed Below - COPYRIGHT 2017,2018 */
/* [+] International Business Machines Corp. */
/* */
/* */
@@ -61,19 +61,37 @@ bool check_str_non_tsv_parity_workaround(const fapi2::Target<fapi2::TARGET_TYPE_
const uint64_t i_idle_power_control)
{
const auto l_less_than_dd2 = chip_ec_nimbus_lt_2_0(i_target);
+ uint8_t l_hybrid[MAX_DIMM_PER_PORT] = {};
+ uint8_t l_stack_type[MAX_DIMM_PER_PORT] = {};
+ bool l_tsv = false;
+ bool l_str_enabled = false;
+ bool l_is_nvdimm = false;
+
+ // Figure out if any hybrid memory is plugged
+ FAPI_TRY(mss::eff_hybrid(i_target, l_hybrid));
+
+ // If hybrid memory is plugged, what kind?
+ // Checking the first dimm here is enough as the plug rules
+ // only allow single drop for NVDIMM
+ if (l_hybrid[0] == fapi2::ENUM_ATTR_EFF_HYBRID_IS_HYBRID)
+ {
+ uint8_t l_hybrid_mem_type[MAX_DIMM_PER_PORT] = {};
+ FAPI_TRY(mss::eff_hybrid_memory_type(i_target, l_hybrid_mem_type));
+ l_is_nvdimm = (l_hybrid_mem_type[0] == fapi2::ENUM_ATTR_EFF_HYBRID_MEMORY_TYPE_NVDIMM);
+ }
// If either STR is enabled, STR is enabled for the whole system
// Per the power thermal team, we only need to check PD_AND_STR and PD_AND_STR_CLK_STOP
- const bool l_str_enabled = (i_power_control == fapi2::ENUM_ATTR_MSS_MRW_POWER_CONTROL_REQUESTED_PD_AND_STR ||
- i_power_control == fapi2::ENUM_ATTR_MSS_MRW_POWER_CONTROL_REQUESTED_PD_AND_STR_CLK_STOP) ||
- (i_idle_power_control == fapi2::ENUM_ATTR_MSS_MRW_IDLE_POWER_CONTROL_REQUESTED_PD_AND_STR ||
- i_idle_power_control == fapi2::ENUM_ATTR_MSS_MRW_IDLE_POWER_CONTROL_REQUESTED_PD_AND_STR_CLK_STOP);
+ // If nvdimm is plugged, STR is also needed
+ l_str_enabled = (i_power_control == fapi2::ENUM_ATTR_MSS_MRW_POWER_CONTROL_REQUESTED_PD_AND_STR ||
+ i_power_control == fapi2::ENUM_ATTR_MSS_MRW_POWER_CONTROL_REQUESTED_PD_AND_STR_CLK_STOP) ||
+ (i_idle_power_control == fapi2::ENUM_ATTR_MSS_MRW_IDLE_POWER_CONTROL_REQUESTED_PD_AND_STR ||
+ i_idle_power_control == fapi2::ENUM_ATTR_MSS_MRW_IDLE_POWER_CONTROL_REQUESTED_PD_AND_STR_CLK_STOP) ||
+ l_is_nvdimm;
// Now checks whether the DIMM's are TSV
// Note: eff_config plug rules will require that the whole MCA either have TSV or non-TSV DIMMs
// As such, it is fine to just check DIMM0 for if it is a TSV DIMM or not
- uint8_t l_stack_type[MAX_DIMM_PER_PORT] = {};
- bool l_tsv = false;
FAPI_TRY(mss::eff_prim_stack_type(i_target, l_stack_type));
// If DIMM0 is a TSV, set to true (DIMM0 has to exist and needs to equal DIMM0 if it's 3DS)
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