Updates training advanced and adds custom WR CTR

Breaks apart and reorganizes training advanced code
Adds custom pattern WR CTR in training advanced
Updates custom WR/RD patterns for characterization data

Change-Id: I3fc6e515f0ae2f853ce53a198a82b7513da4eea5
CQ:SW411492
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50118
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Dev-Ready: STEPHEN GLANCY <sglancy@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Louis Stermole <stermole@us.ibm.com>
Reviewed-by: ANDRE A. MARIN <aamarin@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50141
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>

14 files changed, 1061 insertions, 115 deletions

diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/eff_dimm.C b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/eff_dimm.C
index f6e77862b..ff2ffda69 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/eff_dimm.C
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/eff_dimm.C
@@ -5078,6 +5078,31 @@ fapi_try_exit:
 }
 
 ///
+/// @brief Determines and sets the ATTR_MSS_CUSTOM_TRAINING_ADV_WR_PATTERN settings
+/// @return fapi2::FAPI2_RC_SUCCESS if okay
+/// @note overwrite the attribute to default values if it's set to 0
+///
+fapi2::ReturnCode eff_dimm::training_adv_wr_pattern()
+{
+    uint8_t l_special_patterns [PORTS_PER_MCS] = {};
+    FAPI_TRY( custom_training_adv_wr_pattern( iv_mcs, &(l_special_patterns[0])) );
+
+    // Let's set the backup pattern as well
+    if ( l_special_patterns[mss::index(iv_mca)] == 0)
+    {
+        l_special_patterns[mss::index(iv_mca)] = fapi2::ENUM_ATTR_MSS_CUSTOM_TRAINING_ADV_WR_PATTERN_DEFAULT;
+
+        FAPI_INF("%s setting training_adv_backup_pattern as 0x%02x", mss::c_str(iv_mca),
+                 l_special_patterns[mss::index(iv_mca)]);
+
+        FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_MSS_CUSTOM_TRAINING_ADV_WR_PATTERN, iv_mcs, l_special_patterns) );
+    }
+
+fapi_try_exit:
+    return fapi2::current_err;
+}
+
+///
 /// @brief Determines and sets the cal_step_enable values
 /// @return fapi2::FAPI2_RC_SUCCESS if okay
 ///
@@ -5087,13 +5112,15 @@ fapi2::ReturnCode eff_dimm::cal_step_enable()
             RUN_CAL_SKIP_WR_RD_2D_VREF : RUN_ALL_CAL_STEPS);
 
     // We only run draminit training advance on DD2 modules
-    l_cal_step_value = l_cal_step_value.writeBit<mss::TRAINING_ADV>( !mss::chip_ec_nimbus_lt_2_0(iv_mcs) );
+    constexpr uint64_t NUM_TRAIN_ADV = 2;
+    l_cal_step_value = l_cal_step_value.writeBit<mss::TRAINING_ADV_RD, NUM_TRAIN_ADV>( !mss::chip_ec_nimbus_lt_2_0(
+                           iv_mcs) );
 
     FAPI_DBG("%s %s running HW VREF cal. cal_step value: 0x%08x VREF, running training advance %s",
              mss::c_str(iv_mcs),
              mss::chip_ec_feature_skip_hw_vref_cal(iv_mcs) ? "not" : "",
              l_cal_step_value,
-             l_cal_step_value.getBit<mss::TRAINING_ADV>() ? "yes" : "no");
+             l_cal_step_value.getBit<mss::TRAINING_ADV_RD>() ? "yes" : "no");
 
     // Sets up the vector
     std::vector<uint32_t> l_cal_step(PORTS_PER_MCS, l_cal_step_value);
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/eff_dimm.H b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/eff_dimm.H
index 9b8b1780d..3eb69f099 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/eff_dimm.H
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/eff_dimm.H
@@ -785,6 +785,13 @@ class eff_dimm
         fapi2::ReturnCode training_adv_backup_pattern();
 
         ///
+        /// @brief Determines and sets the ATTR_MSS_CUSTOM_TRAINING_ADV_WR_PATTERN settings
+        /// @return fapi2::FAPI2_RC_SUCCESS if okay
+        /// @note overwrite the attribute to default values if it's set to 0
+        ///
+        fapi2::ReturnCode training_adv_wr_pattern();
+
+        ///
         /// @brief Determines and sets ATTR_MSS_PHY_SEQ_REFRESH_
         /// @return fapi2::FAPI2_RC_SUCCESS if okay
         ///
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/mss_attribute_accessors.H b/src/import/chips/p9/procedures/hwp/memory/lib/mss_attribute_accessors.H
index fa1683bd2..783fd05aa 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/mss_attribute_accessors.H
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/mss_attribute_accessors.H
@@ -9273,12 +9273,13 @@ fapi_try_exit:
 /// MRD - Fine (LRDIMM) [5] WR_LEVEL [6] INITIAL_PAT_WR [7] WR_VREF_LATCH [8] DWL
 /// (LRDIMM) [9] MWD - Coarse (LRDIMM) [10] MWD - Fine (LRDIMM) [11] HWL (LRDIMM)
 /// [12] DQS_ALIGN [13] RDCLK_ALIGN [14] READ_CTR_2D_VREF [15] READ_CTR [16]
-/// WRITE_CTR_2D_VREF [17] WRITE_CTR [18] COARSE_WR [19] COARSE_RD [20] TRAINING_ADV
-/// Only set for DD2.* machines [21]:[31] Reserved for future use COARSE_WR and
-/// COARSE_RD will be consumed together to form COARSE_LVL. WRITE_CTR will be run,
-/// even if only WRITE_CTR_2D_VREF is enabled, as the WR 2D VREF HW cal depends upon
-/// WRITE_CTR 1D to function. Note: LRDIMM steps will only be enabled for LRDIMMs
-/// and won't run on
+/// WRITE_CTR_2D_VREF [17] WRITE_CTR [18] COARSE_WR [19] COARSE_RD [20]
+/// TRAINING_ADV_RD Only set for DD2.* machines [21] TRAINING_ADV_WR Only set for
+/// DD2.* machines [22]:[31] Reserved for future use COARSE_WR and COARSE_RD will be
+/// consumed together to form COARSE_LVL. WRITE_CTR will be run, even if only
+/// WRITE_CTR_2D_VREF is enabled, as the WR 2D VREF HW cal depends upon WRITE_CTR 1D
+/// to function. Note: LRDIMM steps will only be enabled for LRDIMMs and won't run
+/// on
 /// RDIMMs.
 ///
 inline fapi2::ReturnCode cal_step_enable(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target, uint32_t& o_value)
@@ -9306,12 +9307,13 @@ fapi_try_exit:
 /// MRD - Fine (LRDIMM) [5] WR_LEVEL [6] INITIAL_PAT_WR [7] WR_VREF_LATCH [8] DWL
 /// (LRDIMM) [9] MWD - Coarse (LRDIMM) [10] MWD - Fine (LRDIMM) [11] HWL (LRDIMM)
 /// [12] DQS_ALIGN [13] RDCLK_ALIGN [14] READ_CTR_2D_VREF [15] READ_CTR [16]
-/// WRITE_CTR_2D_VREF [17] WRITE_CTR [18] COARSE_WR [19] COARSE_RD [20] TRAINING_ADV
-/// Only set for DD2.* machines [21]:[31] Reserved for future use COARSE_WR and
-/// COARSE_RD will be consumed together to form COARSE_LVL. WRITE_CTR will be run,
-/// even if only WRITE_CTR_2D_VREF is enabled, as the WR 2D VREF HW cal depends upon
-/// WRITE_CTR 1D to function. Note: LRDIMM steps will only be enabled for LRDIMMs
-/// and won't run on
+/// WRITE_CTR_2D_VREF [17] WRITE_CTR [18] COARSE_WR [19] COARSE_RD [20]
+/// TRAINING_ADV_RD Only set for DD2.* machines [21] TRAINING_ADV_WR Only set for
+/// DD2.* machines [22]:[31] Reserved for future use COARSE_WR and COARSE_RD will be
+/// consumed together to form COARSE_LVL. WRITE_CTR will be run, even if only
+/// WRITE_CTR_2D_VREF is enabled, as the WR 2D VREF HW cal depends upon WRITE_CTR 1D
+/// to function. Note: LRDIMM steps will only be enabled for LRDIMMs and won't run
+/// on
 /// RDIMMs.
 ///
 inline fapi2::ReturnCode cal_step_enable(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, uint32_t& o_value)
@@ -9340,12 +9342,13 @@ fapi_try_exit:
 /// MRD - Fine (LRDIMM) [5] WR_LEVEL [6] INITIAL_PAT_WR [7] WR_VREF_LATCH [8] DWL
 /// (LRDIMM) [9] MWD - Coarse (LRDIMM) [10] MWD - Fine (LRDIMM) [11] HWL (LRDIMM)
 /// [12] DQS_ALIGN [13] RDCLK_ALIGN [14] READ_CTR_2D_VREF [15] READ_CTR [16]
-/// WRITE_CTR_2D_VREF [17] WRITE_CTR [18] COARSE_WR [19] COARSE_RD [20] TRAINING_ADV
-/// Only set for DD2.* machines [21]:[31] Reserved for future use COARSE_WR and
-/// COARSE_RD will be consumed together to form COARSE_LVL. WRITE_CTR will be run,
-/// even if only WRITE_CTR_2D_VREF is enabled, as the WR 2D VREF HW cal depends upon
-/// WRITE_CTR 1D to function. Note: LRDIMM steps will only be enabled for LRDIMMs
-/// and won't run on
+/// WRITE_CTR_2D_VREF [17] WRITE_CTR [18] COARSE_WR [19] COARSE_RD [20]
+/// TRAINING_ADV_RD Only set for DD2.* machines [21] TRAINING_ADV_WR Only set for
+/// DD2.* machines [22]:[31] Reserved for future use COARSE_WR and COARSE_RD will be
+/// consumed together to form COARSE_LVL. WRITE_CTR will be run, even if only
+/// WRITE_CTR_2D_VREF is enabled, as the WR 2D VREF HW cal depends upon WRITE_CTR 1D
+/// to function. Note: LRDIMM steps will only be enabled for LRDIMMs and won't run
+/// on
 /// RDIMMs.
 ///
 inline fapi2::ReturnCode cal_step_enable(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target, uint32_t* o_array)
@@ -9375,7 +9378,7 @@ fapi_try_exit:
 /// @note Generated by gen_accessors.pl generateParameters (D)
 /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
 /// @note  Special training pattern used in draminit_training_advance. Used for custom
-/// pattern write There can be two patterns used here. This attribute is before
+/// pattern read There can be two patterns used here. This attribute is before
 /// swizzling for endianness of the registers. CODE WILL SWIZZLE FOR THE SYSTEM The
 /// first 0-15 bits are for PATTERN0, bits 16-32 are for PATTERN1. If this attribute
 /// is set to 0, using the default values of: 0x13EC for PATTERN0 0x02FD for
@@ -9405,7 +9408,7 @@ fapi_try_exit:
 /// @note Generated by gen_accessors.pl generateParameters (D.1)
 /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
 /// @note  Special training pattern used in draminit_training_advance. Used for custom
-/// pattern write There can be two patterns used here. This attribute is before
+/// pattern read There can be two patterns used here. This attribute is before
 /// swizzling for endianness of the registers. CODE WILL SWIZZLE FOR THE SYSTEM The
 /// first 0-15 bits are for PATTERN0, bits 16-32 are for PATTERN1. If this attribute
 /// is set to 0, using the default values of: 0x13EC for PATTERN0 0x02FD for
@@ -9436,7 +9439,7 @@ fapi_try_exit:
 /// @note Generated by gen_accessors.pl generateParameters (E)
 /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
 /// @note  Special training pattern used in draminit_training_advance. Used for custom
-/// pattern write There can be two patterns used here. This attribute is before
+/// pattern read There can be two patterns used here. This attribute is before
 /// swizzling for endianness of the registers. CODE WILL SWIZZLE FOR THE SYSTEM The
 /// first 0-15 bits are for PATTERN0, bits 16-32 are for PATTERN1. If this attribute
 /// is set to 0, using the default values of: 0x13EC for PATTERN0 0x02FD for
@@ -9470,7 +9473,7 @@ fapi_try_exit:
 /// @param[out] ref to the value uint32_t
 /// @note Generated by gen_accessors.pl generateParameters (D)
 /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
-/// @note  Special training backup pattern Used for custom_pattern_write in
+/// @note  Special training backup pattern Used for custom_pattern_read in
 /// draminit_training_advance. If the main patterns fail, the code will try running
 /// this pattern Used for read centering There can be two patterns used here. This
 /// attribute is before swizzling for endianness of the registers. CODE WILL SWIZZLE
@@ -9501,7 +9504,7 @@ fapi_try_exit:
 /// @param[out] ref to the value uint32_t
 /// @note Generated by gen_accessors.pl generateParameters (D.1)
 /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
-/// @note  Special training backup pattern Used for custom_pattern_write in
+/// @note  Special training backup pattern Used for custom_pattern_read in
 /// draminit_training_advance. If the main patterns fail, the code will try running
 /// this pattern Used for read centering There can be two patterns used here. This
 /// attribute is before swizzling for endianness of the registers. CODE WILL SWIZZLE
@@ -9533,7 +9536,7 @@ fapi_try_exit:
 /// @param[out] uint32_t* memory to store the value
 /// @note Generated by gen_accessors.pl generateParameters (E)
 /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
-/// @note  Special training backup pattern Used for custom_pattern_write in
+/// @note  Special training backup pattern Used for custom_pattern_read in
 /// draminit_training_advance. If the main patterns fail, the code will try running
 /// this pattern Used for read centering There can be two patterns used here. This
 /// attribute is before swizzling for endianness of the registers. CODE WILL SWIZZLE
@@ -9564,6 +9567,99 @@ fapi_try_exit:
 }
 
 ///
+/// @brief ATTR_MSS_CUSTOM_TRAINING_ADV_WR_PATTERN getter
+/// @param[in] const ref to the fapi2::Target<fapi2::TARGET_TYPE_MCA>
+/// @param[out] ref to the value uint8_t
+/// @note Generated by gen_accessors.pl generateParameters (D)
+/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
+/// @note  Special training pattern used in draminit_training_advance. Used for custom
+/// pattern write Due to hardware limitations, only one 8-bit pattern can be used
+/// This attribute is before swizzling for endianness of the registers. CODE WILL
+/// SWIZZLE FOR THE SYSTEM If this attribute is set to 0, using the default values
+/// of: 0x9A Set to default in
+/// eff_config
+///
+inline fapi2::ReturnCode custom_training_adv_wr_pattern(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target,
+        uint8_t& o_value)
+{
+    uint8_t l_value[2];
+
+    FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_CUSTOM_TRAINING_ADV_WR_PATTERN, i_target.getParent<fapi2::TARGET_TYPE_MCS>(),
+                            l_value) );
+    o_value = l_value[mss::index(i_target)];
+    return fapi2::current_err;
+
+fapi_try_exit:
+    FAPI_ERR("failed accessing ATTR_MSS_CUSTOM_TRAINING_ADV_WR_PATTERN: 0x%lx (target: %s)",
+             uint64_t(fapi2::current_err), mss::c_str(i_target));
+    return fapi2::current_err;
+}
+
+///
+/// @brief ATTR_MSS_CUSTOM_TRAINING_ADV_WR_PATTERN getter
+/// @param[in] const ref to the fapi2::Target<fapi2::TARGET_TYPE_DIMM>
+/// @param[out] ref to the value uint8_t
+/// @note Generated by gen_accessors.pl generateParameters (D.1)
+/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
+/// @note  Special training pattern used in draminit_training_advance. Used for custom
+/// pattern write Due to hardware limitations, only one 8-bit pattern can be used
+/// This attribute is before swizzling for endianness of the registers. CODE WILL
+/// SWIZZLE FOR THE SYSTEM If this attribute is set to 0, using the default values
+/// of: 0x9A Set to default in
+/// eff_config
+///
+inline fapi2::ReturnCode custom_training_adv_wr_pattern(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
+        uint8_t& o_value)
+{
+    uint8_t l_value[2];
+    auto l_mca = i_target.getParent<fapi2::TARGET_TYPE_MCA>();
+
+    FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_CUSTOM_TRAINING_ADV_WR_PATTERN, l_mca.getParent<fapi2::TARGET_TYPE_MCS>(),
+                            l_value) );
+    o_value = l_value[mss::index(l_mca)];
+    return fapi2::current_err;
+
+fapi_try_exit:
+    FAPI_ERR("failed accessing ATTR_MSS_CUSTOM_TRAINING_ADV_WR_PATTERN: 0x%lx (target: %s)",
+             uint64_t(fapi2::current_err), mss::c_str(i_target));
+    return fapi2::current_err;
+}
+
+///
+/// @brief ATTR_MSS_CUSTOM_TRAINING_ADV_WR_PATTERN getter
+/// @param[in] const ref to the fapi2::Target<fapi2::TARGET_TYPE_MCS>
+/// @param[out] uint8_t* memory to store the value
+/// @note Generated by gen_accessors.pl generateParameters (E)
+/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
+/// @note  Special training pattern used in draminit_training_advance. Used for custom
+/// pattern write Due to hardware limitations, only one 8-bit pattern can be used
+/// This attribute is before swizzling for endianness of the registers. CODE WILL
+/// SWIZZLE FOR THE SYSTEM If this attribute is set to 0, using the default values
+/// of: 0x9A Set to default in
+/// eff_config
+///
+inline fapi2::ReturnCode custom_training_adv_wr_pattern(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
+        uint8_t* o_array)
+{
+    if (o_array == nullptr)
+    {
+        FAPI_ERR("nullptr passed to attribute accessor %s", __func__);
+        return fapi2::FAPI2_RC_INVALID_PARAMETER;
+    }
+
+    uint8_t l_value[2];
+
+    FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_CUSTOM_TRAINING_ADV_WR_PATTERN, i_target, l_value) );
+    memcpy(o_array, &l_value, 2);
+    return fapi2::current_err;
+
+fapi_try_exit:
+    FAPI_ERR("failed accessing ATTR_MSS_CUSTOM_TRAINING_ADV_WR_PATTERN: 0x%lx (target: %s)",
+             uint64_t(fapi2::current_err), mss::c_str(i_target));
+    return fapi2::current_err;
+}
+
+///
 /// @brief ATTR_MSS_VREF_CAL_ENABLE getter
 /// @param[in] const ref to the fapi2::Target<fapi2::TARGET_TYPE_MCA>
 /// @param[out] ref to the value uint16_t
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/phy/ddr_phy.C b/src/import/chips/p9/procedures/hwp/memory/lib/phy/ddr_phy.C
index 564ed5c54..6c085ce43 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/phy/ddr_phy.C
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/phy/ddr_phy.C
@@ -5,7 +5,7 @@
 /*                                                                        */
 /* OpenPOWER HostBoot Project                                             */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2015,2017                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2018                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
 /*                                                                        */
@@ -1552,6 +1552,49 @@ fapi_try_exit:
 }
 
 ///
+/// @brief Set the custom pattern
+/// @param[in] i_target the port target
+/// @return FAPI2_RC_SUCCESS iff setup was successful
+///
+template<>
+fapi2::ReturnCode configure_custom_wr_pattern( const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target )
+{
+    // Pattern constexprs
+    constexpr uint64_t PATTERN_LEN = 8;
+    constexpr uint64_t PATTERN_COPY0_POS = 0;
+    constexpr uint64_t PATTERN_COPY1_POS = PATTERN_LEN + PATTERN_COPY0_POS;
+    constexpr uint64_t PATTERN_COPY2_POS = PATTERN_LEN + PATTERN_COPY1_POS;
+    constexpr uint64_t PATTERN_COPY3_POS = PATTERN_LEN + PATTERN_COPY2_POS;
+
+    uint8_t l_pattern = 0;
+    fapi2::buffer<uint32_t> l_buff;
+    uint32_t l_swizzled = 0;
+
+    // Set the custom patterns for training advance
+    // So first get the pattern from the attribute and then put it into the register
+    // The custom write pattern is only 8 bits wide
+    // We want to run it across all nibbles in the DP (one byte of a pattern per nibble in the DP)
+    // So, we need to copy it four times into the buffer
+
+    FAPI_TRY( mss::custom_training_adv_wr_pattern( i_target, l_pattern) );
+    l_buff.insertFromRight<PATTERN_COPY0_POS, PATTERN_LEN>(l_pattern)
+    .insertFromRight<PATTERN_COPY1_POS, PATTERN_LEN>(l_pattern)
+    .insertFromRight<PATTERN_COPY2_POS, PATTERN_LEN>(l_pattern)
+    .insertFromRight<PATTERN_COPY3_POS, PATTERN_LEN>(l_pattern);
+    FAPI_TRY( mss::seq::swizzle_mpr_pattern(l_buff, l_swizzled) );
+
+    FAPI_INF("%s the patterns before swizzle are 0x%08x and after 0x%08x",
+             mss::c_str(i_target),
+             l_buff,
+             l_swizzled);
+
+    FAPI_TRY( mss::seq::setup_rd_wr_data( i_target, l_swizzled) );
+
+fapi_try_exit:
+    return fapi2::current_err;
+}
+
+///
 /// @brief Flush the output drivers
 /// @param[in] i_target the target associated with the phy reset sequence
 /// @return FAPI2_RC_SUCCESS iff setup was successful
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/phy/ddr_phy.H b/src/import/chips/p9/procedures/hwp/memory/lib/phy/ddr_phy.H
index d56af96cd..7c69d4331 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/phy/ddr_phy.H
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/phy/ddr_phy.H
@@ -5,7 +5,7 @@
 /*                                                                        */
 /* OpenPOWER HostBoot Project                                             */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2015,2017                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2018                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
 /*                                                                        */
@@ -408,6 +408,13 @@ fapi2::ReturnCode rank_pair_primary_to_dimm(const fapi2::Target<T>& i_target, co
 ///
 template<fapi2::TargetType T>
 fapi2::ReturnCode configure_custom_pattern( const fapi2::Target<T>& i_target );
+///
+/// @brief Set the custom write pattern
+/// @param[in] i_target the port target
+/// @return FAPI2_RC_SUCCESS iff setup was successful
+///
+template<fapi2::TargetType T>
+fapi2::ReturnCode configure_custom_wr_pattern( const fapi2::Target<T>& i_target );
 
 ///
 /// @brief Handle draminit_training cal fails
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/phy/dp16.C b/src/import/chips/p9/procedures/hwp/memory/lib/phy/dp16.C
index 5522ec472..975c0ae6b 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/phy/dp16.C
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/phy/dp16.C
@@ -1415,6 +1415,442 @@ const std::vector< std::vector<uint64_t> > dp16Traits<TARGET_TYPE_MCA>::WR_DQ_DE
     },
 };
 
+const std::vector<std::vector<uint64_t>> dp16Traits<TARGET_TYPE_MCA>::WR_DELAY_REG
+{
+    // RP0
+    {
+        // DP0
+        MCA_DP16_WR_DELAY_VALUE_0_RP0_REG_P0_0,
+        MCA_DP16_WR_DELAY_VALUE_1_RP0_REG_P0_0,
+        MCA_DP16_WR_DELAY_VALUE_2_RP0_REG_P0_0,
+        MCA_DP16_WR_DELAY_VALUE_3_RP0_REG_P0_0,
+        MCA_DP16_WR_DELAY_VALUE_4_RP0_REG_P0_0,
+        MCA_DP16_WR_DELAY_VALUE_5_RP0_REG_P0_0,
+        MCA_DP16_WR_DELAY_VALUE_6_RP0_REG_P0_0,
+        MCA_DP16_WR_DELAY_VALUE_7_RP0_REG_P0_0,
+        MCA_DP16_WR_DELAY_VALUE_8_RP0_REG_P0_0,
+        MCA_DP16_WR_DELAY_VALUE_9_RP0_REG_P0_0,
+        MCA_DP16_WR_DELAY_VALUE_10_RP0_REG_P0_0,
+        MCA_DP16_WR_DELAY_VALUE_11_RP0_REG_P0_0,
+        MCA_DP16_WR_DELAY_VALUE_12_RP0_REG_P0_0,
+        MCA_DP16_WR_DELAY_VALUE_13_RP0_REG_P0_0,
+        MCA_DP16_WR_DELAY_VALUE_14_RP0_REG_P0_0,
+        MCA_DP16_WR_DELAY_VALUE_15_RP0_REG_P0_0,
+        MCA_DP16_WR_DELAY_VALUE_16_RP0_REG_P0_0,
+        MCA_DP16_WR_DELAY_VALUE_18_RP0_REG_P0_0,
+        MCA_DP16_WR_DELAY_VALUE_20_RP0_REG_P0_0,
+        MCA_DP16_WR_DELAY_VALUE_22_RP0_REG_P0_0,
+        // DP1
+        MCA_DP16_WR_DELAY_VALUE_0_RP0_REG_P0_1,
+        MCA_DP16_WR_DELAY_VALUE_1_RP0_REG_P0_1,
+        MCA_DP16_WR_DELAY_VALUE_2_RP0_REG_P0_1,
+        MCA_DP16_WR_DELAY_VALUE_3_RP0_REG_P0_1,
+        MCA_DP16_WR_DELAY_VALUE_4_RP0_REG_P0_1,
+        MCA_DP16_WR_DELAY_VALUE_5_RP0_REG_P0_1,
+        MCA_DP16_WR_DELAY_VALUE_6_RP0_REG_P0_1,
+        MCA_DP16_WR_DELAY_VALUE_7_RP0_REG_P0_1,
+        MCA_DP16_WR_DELAY_VALUE_8_RP0_REG_P0_1,
+        MCA_DP16_WR_DELAY_VALUE_9_RP0_REG_P0_1,
+        MCA_DP16_WR_DELAY_VALUE_10_RP0_REG_P0_1,
+        MCA_DP16_WR_DELAY_VALUE_11_RP0_REG_P0_1,
+        MCA_DP16_WR_DELAY_VALUE_12_RP0_REG_P0_1,
+        MCA_DP16_WR_DELAY_VALUE_13_RP0_REG_P0_1,
+        MCA_DP16_WR_DELAY_VALUE_14_RP0_REG_P0_1,
+        MCA_DP16_WR_DELAY_VALUE_15_RP0_REG_P0_1,
+        MCA_DP16_WR_DELAY_VALUE_16_RP0_REG_P0_1,
+        MCA_DP16_WR_DELAY_VALUE_18_RP0_REG_P0_1,
+        MCA_DP16_WR_DELAY_VALUE_20_RP0_REG_P0_1,
+        MCA_DP16_WR_DELAY_VALUE_22_RP0_REG_P0_1,
+        // DP2
+        MCA_DP16_WR_DELAY_VALUE_0_RP0_REG_P0_2,
+        MCA_DP16_WR_DELAY_VALUE_1_RP0_REG_P0_2,
+        MCA_DP16_WR_DELAY_VALUE_2_RP0_REG_P0_2,
+        MCA_DP16_WR_DELAY_VALUE_3_RP0_REG_P0_2,
+        MCA_DP16_WR_DELAY_VALUE_4_RP0_REG_P0_2,
+        MCA_DP16_WR_DELAY_VALUE_5_RP0_REG_P0_2,
+        MCA_DP16_WR_DELAY_VALUE_6_RP0_REG_P0_2,
+        MCA_DP16_WR_DELAY_VALUE_7_RP0_REG_P0_2,
+        MCA_DP16_WR_DELAY_VALUE_8_RP0_REG_P0_2,
+        MCA_DP16_WR_DELAY_VALUE_9_RP0_REG_P0_2,
+        MCA_DP16_WR_DELAY_VALUE_10_RP0_REG_P0_2,
+        MCA_DP16_WR_DELAY_VALUE_11_RP0_REG_P0_2,
+        MCA_DP16_WR_DELAY_VALUE_12_RP0_REG_P0_2,
+        MCA_DP16_WR_DELAY_VALUE_13_RP0_REG_P0_2,
+        MCA_DP16_WR_DELAY_VALUE_14_RP0_REG_P0_2,
+        MCA_DP16_WR_DELAY_VALUE_15_RP0_REG_P0_2,
+        MCA_DP16_WR_DELAY_VALUE_16_RP0_REG_P0_2,
+        MCA_DP16_WR_DELAY_VALUE_18_RP0_REG_P0_2,
+        MCA_DP16_WR_DELAY_VALUE_20_RP0_REG_P0_2,
+        MCA_DP16_WR_DELAY_VALUE_22_RP0_REG_P0_2,
+        // DP3
+        MCA_DP16_WR_DELAY_VALUE_0_RP0_REG_P0_3,
+        MCA_DP16_WR_DELAY_VALUE_1_RP0_REG_P0_3,
+        MCA_DP16_WR_DELAY_VALUE_2_RP0_REG_P0_3,
+        MCA_DP16_WR_DELAY_VALUE_3_RP0_REG_P0_3,
+        MCA_DP16_WR_DELAY_VALUE_4_RP0_REG_P0_3,
+        MCA_DP16_WR_DELAY_VALUE_5_RP0_REG_P0_3,
+        MCA_DP16_WR_DELAY_VALUE_6_RP0_REG_P0_3,
+        MCA_DP16_WR_DELAY_VALUE_7_RP0_REG_P0_3,
+        MCA_DP16_WR_DELAY_VALUE_8_RP0_REG_P0_3,
+        MCA_DP16_WR_DELAY_VALUE_9_RP0_REG_P0_3,
+        MCA_DP16_WR_DELAY_VALUE_10_RP0_REG_P0_3,
+        MCA_DP16_WR_DELAY_VALUE_11_RP0_REG_P0_3,
+        MCA_DP16_WR_DELAY_VALUE_12_RP0_REG_P0_3,
+        MCA_DP16_WR_DELAY_VALUE_13_RP0_REG_P0_3,
+        MCA_DP16_WR_DELAY_VALUE_14_RP0_REG_P0_3,
+        MCA_DP16_WR_DELAY_VALUE_15_RP0_REG_P0_3,
+        MCA_DP16_WR_DELAY_VALUE_16_RP0_REG_P0_3,
+        MCA_DP16_WR_DELAY_VALUE_18_RP0_REG_P0_3,
+        MCA_DP16_WR_DELAY_VALUE_20_RP0_REG_P0_3,
+        MCA_DP16_WR_DELAY_VALUE_22_RP0_REG_P0_3,
+        // DP4
+        MCA_DP16_WR_DELAY_VALUE_0_RP0_REG_P0_4,
+        MCA_DP16_WR_DELAY_VALUE_1_RP0_REG_P0_4,
+        MCA_DP16_WR_DELAY_VALUE_2_RP0_REG_P0_4,
+        MCA_DP16_WR_DELAY_VALUE_3_RP0_REG_P0_4,
+        MCA_DP16_WR_DELAY_VALUE_4_RP0_REG_P0_4,
+        MCA_DP16_WR_DELAY_VALUE_5_RP0_REG_P0_4,
+        MCA_DP16_WR_DELAY_VALUE_6_RP0_REG_P0_4,
+        MCA_DP16_WR_DELAY_VALUE_7_RP0_REG_P0_4,
+        MCA_DP16_WR_DELAY_VALUE_8_RP0_REG_P0_4,
+        MCA_DP16_WR_DELAY_VALUE_9_RP0_REG_P0_4,
+        MCA_DP16_WR_DELAY_VALUE_10_RP0_REG_P0_4,
+        MCA_DP16_WR_DELAY_VALUE_11_RP0_REG_P0_4,
+        MCA_DP16_WR_DELAY_VALUE_12_RP0_REG_P0_4,
+        MCA_DP16_WR_DELAY_VALUE_13_RP0_REG_P0_4,
+        MCA_DP16_WR_DELAY_VALUE_14_RP0_REG_P0_4,
+        MCA_DP16_WR_DELAY_VALUE_15_RP0_REG_P0_4,
+        MCA_DP16_WR_DELAY_VALUE_16_RP0_REG_P0_4,
+        MCA_DP16_WR_DELAY_VALUE_18_RP0_REG_P0_4,
+        MCA_DP16_WR_DELAY_VALUE_20_RP0_REG_P0_4,
+        MCA_DP16_WR_DELAY_VALUE_22_RP0_REG_P0_4,
+    },
+    // RP1
+    {
+        // DP0
+        MCA_DP16_WR_DELAY_VALUE_0_RP1_REG_P0_0,
+        MCA_DP16_WR_DELAY_VALUE_1_RP1_REG_P0_0,
+        MCA_DP16_WR_DELAY_VALUE_2_RP1_REG_P0_0,
+        MCA_DP16_WR_DELAY_VALUE_3_RP1_REG_P0_0,
+        MCA_DP16_WR_DELAY_VALUE_4_RP1_REG_P0_0,
+        MCA_DP16_WR_DELAY_VALUE_5_RP1_REG_P0_0,
+        MCA_DP16_WR_DELAY_VALUE_6_RP1_REG_P0_0,
+        MCA_DP16_WR_DELAY_VALUE_7_RP1_REG_P0_0,
+        MCA_DP16_WR_DELAY_VALUE_8_RP1_REG_P0_0,
+        MCA_DP16_WR_DELAY_VALUE_9_RP1_REG_P0_0,
+        MCA_DP16_WR_DELAY_VALUE_10_RP1_REG_P0_0,
+        MCA_DP16_WR_DELAY_VALUE_11_RP1_REG_P0_0,
+        MCA_DP16_WR_DELAY_VALUE_12_RP1_REG_P0_0,
+        MCA_DP16_WR_DELAY_VALUE_13_RP1_REG_P0_0,
+        MCA_DP16_WR_DELAY_VALUE_14_RP1_REG_P0_0,
+        MCA_DP16_WR_DELAY_VALUE_15_RP1_REG_P0_0,
+        MCA_DP16_WR_DELAY_VALUE_16_RP1_REG_P0_0,
+        MCA_DP16_WR_DELAY_VALUE_18_RP1_REG_P0_0,
+        MCA_DP16_WR_DELAY_VALUE_20_RP1_REG_P0_0,
+        MCA_DP16_WR_DELAY_VALUE_22_RP1_REG_P0_0,
+        // DP1
+        MCA_DP16_WR_DELAY_VALUE_0_RP1_REG_P0_1,
+        MCA_DP16_WR_DELAY_VALUE_1_RP1_REG_P0_1,
+        MCA_DP16_WR_DELAY_VALUE_2_RP1_REG_P0_1,
+        MCA_DP16_WR_DELAY_VALUE_3_RP1_REG_P0_1,
+        MCA_DP16_WR_DELAY_VALUE_4_RP1_REG_P0_1,
+        MCA_DP16_WR_DELAY_VALUE_5_RP1_REG_P0_1,
+        MCA_DP16_WR_DELAY_VALUE_6_RP1_REG_P0_1,
+        MCA_DP16_WR_DELAY_VALUE_7_RP1_REG_P0_1,
+        MCA_DP16_WR_DELAY_VALUE_8_RP1_REG_P0_1,
+        MCA_DP16_WR_DELAY_VALUE_9_RP1_REG_P0_1,
+        MCA_DP16_WR_DELAY_VALUE_10_RP1_REG_P0_1,
+        MCA_DP16_WR_DELAY_VALUE_11_RP1_REG_P0_1,
+        MCA_DP16_WR_DELAY_VALUE_12_RP1_REG_P0_1,
+        MCA_DP16_WR_DELAY_VALUE_13_RP1_REG_P0_1,
+        MCA_DP16_WR_DELAY_VALUE_14_RP1_REG_P0_1,
+        MCA_DP16_WR_DELAY_VALUE_15_RP1_REG_P0_1,
+        MCA_DP16_WR_DELAY_VALUE_16_RP1_REG_P0_1,
+        MCA_DP16_WR_DELAY_VALUE_18_RP1_REG_P0_1,
+        MCA_DP16_WR_DELAY_VALUE_20_RP1_REG_P0_1,
+        MCA_DP16_WR_DELAY_VALUE_22_RP1_REG_P0_1,
+        // DP2
+        MCA_DP16_WR_DELAY_VALUE_0_RP1_REG_P0_2,
+        MCA_DP16_WR_DELAY_VALUE_1_RP1_REG_P0_2,
+        MCA_DP16_WR_DELAY_VALUE_2_RP1_REG_P0_2,
+        MCA_DP16_WR_DELAY_VALUE_3_RP1_REG_P0_2,
+        MCA_DP16_WR_DELAY_VALUE_4_RP1_REG_P0_2,
+        MCA_DP16_WR_DELAY_VALUE_5_RP1_REG_P0_2,
+        MCA_DP16_WR_DELAY_VALUE_6_RP1_REG_P0_2,
+        MCA_DP16_WR_DELAY_VALUE_7_RP1_REG_P0_2,
+        MCA_DP16_WR_DELAY_VALUE_8_RP1_REG_P0_2,
+        MCA_DP16_WR_DELAY_VALUE_9_RP1_REG_P0_2,
+        MCA_DP16_WR_DELAY_VALUE_10_RP1_REG_P0_2,
+        MCA_DP16_WR_DELAY_VALUE_11_RP1_REG_P0_2,
+        MCA_DP16_WR_DELAY_VALUE_12_RP1_REG_P0_2,
+        MCA_DP16_WR_DELAY_VALUE_13_RP1_REG_P0_2,
+        MCA_DP16_WR_DELAY_VALUE_14_RP1_REG_P0_2,
+        MCA_DP16_WR_DELAY_VALUE_15_RP1_REG_P0_2,
+        MCA_DP16_WR_DELAY_VALUE_16_RP1_REG_P0_2,
+        MCA_DP16_WR_DELAY_VALUE_18_RP1_REG_P0_2,
+        MCA_DP16_WR_DELAY_VALUE_20_RP1_REG_P0_2,
+        MCA_DP16_WR_DELAY_VALUE_22_RP1_REG_P0_2,
+        // DP3
+        MCA_DP16_WR_DELAY_VALUE_0_RP1_REG_P0_3,
+        MCA_DP16_WR_DELAY_VALUE_1_RP1_REG_P0_3,
+        MCA_DP16_WR_DELAY_VALUE_2_RP1_REG_P0_3,
+        MCA_DP16_WR_DELAY_VALUE_3_RP1_REG_P0_3,
+        MCA_DP16_WR_DELAY_VALUE_4_RP1_REG_P0_3,
+        MCA_DP16_WR_DELAY_VALUE_5_RP1_REG_P0_3,
+        MCA_DP16_WR_DELAY_VALUE_6_RP1_REG_P0_3,
+        MCA_DP16_WR_DELAY_VALUE_7_RP1_REG_P0_3,
+        MCA_DP16_WR_DELAY_VALUE_8_RP1_REG_P0_3,
+        MCA_DP16_WR_DELAY_VALUE_9_RP1_REG_P0_3,
+        MCA_DP16_WR_DELAY_VALUE_10_RP1_REG_P0_3,
+        MCA_DP16_WR_DELAY_VALUE_11_RP1_REG_P0_3,
+        MCA_DP16_WR_DELAY_VALUE_12_RP1_REG_P0_3,
+        MCA_DP16_WR_DELAY_VALUE_13_RP1_REG_P0_3,
+        MCA_DP16_WR_DELAY_VALUE_14_RP1_REG_P0_3,
+        MCA_DP16_WR_DELAY_VALUE_15_RP1_REG_P0_3,
+        MCA_DP16_WR_DELAY_VALUE_16_RP1_REG_P0_3,
+        MCA_DP16_WR_DELAY_VALUE_18_RP1_REG_P0_3,
+        MCA_DP16_WR_DELAY_VALUE_20_RP1_REG_P0_3,
+        MCA_DP16_WR_DELAY_VALUE_22_RP1_REG_P0_3,
+        // DP4
+        MCA_DP16_WR_DELAY_VALUE_0_RP1_REG_P0_4,
+        MCA_DP16_WR_DELAY_VALUE_1_RP1_REG_P0_4,
+        MCA_DP16_WR_DELAY_VALUE_2_RP1_REG_P0_4,
+        MCA_DP16_WR_DELAY_VALUE_3_RP1_REG_P0_4,
+        MCA_DP16_WR_DELAY_VALUE_4_RP1_REG_P0_4,
+        MCA_DP16_WR_DELAY_VALUE_5_RP1_REG_P0_4,
+        MCA_DP16_WR_DELAY_VALUE_6_RP1_REG_P0_4,
+        MCA_DP16_WR_DELAY_VALUE_7_RP1_REG_P0_4,
+        MCA_DP16_WR_DELAY_VALUE_8_RP1_REG_P0_4,
+        MCA_DP16_WR_DELAY_VALUE_9_RP1_REG_P0_4,
+        MCA_DP16_WR_DELAY_VALUE_10_RP1_REG_P0_4,
+        MCA_DP16_WR_DELAY_VALUE_11_RP1_REG_P0_4,
+        MCA_DP16_WR_DELAY_VALUE_12_RP1_REG_P0_4,
+        MCA_DP16_WR_DELAY_VALUE_13_RP1_REG_P0_4,
+        MCA_DP16_WR_DELAY_VALUE_14_RP1_REG_P0_4,
+        MCA_DP16_WR_DELAY_VALUE_15_RP1_REG_P0_4,
+        MCA_DP16_WR_DELAY_VALUE_16_RP1_REG_P0_4,
+        MCA_DP16_WR_DELAY_VALUE_18_RP1_REG_P0_4,
+        MCA_DP16_WR_DELAY_VALUE_20_RP1_REG_P0_4,
+        MCA_DP16_WR_DELAY_VALUE_22_RP1_REG_P0_4,
+    },
+    // RP2
+    {
+        // DP0
+        MCA_DP16_WR_DELAY_VALUE_0_RP2_REG_P0_0,
+        MCA_DP16_WR_DELAY_VALUE_1_RP2_REG_P0_0,
+        MCA_DP16_WR_DELAY_VALUE_2_RP2_REG_P0_0,
+        MCA_DP16_WR_DELAY_VALUE_3_RP2_REG_P0_0,
+        MCA_DP16_WR_DELAY_VALUE_4_RP2_REG_P0_0,
+        MCA_DP16_WR_DELAY_VALUE_5_RP2_REG_P0_0,
+        MCA_DP16_WR_DELAY_VALUE_6_RP2_REG_P0_0,
+        MCA_DP16_WR_DELAY_VALUE_7_RP2_REG_P0_0,
+        MCA_DP16_WR_DELAY_VALUE_8_RP2_REG_P0_0,
+        MCA_DP16_WR_DELAY_VALUE_9_RP2_REG_P0_0,
+        MCA_DP16_WR_DELAY_VALUE_10_RP2_REG_P0_0,
+        MCA_DP16_WR_DELAY_VALUE_11_RP2_REG_P0_0,
+        MCA_DP16_WR_DELAY_VALUE_12_RP2_REG_P0_0,
+        MCA_DP16_WR_DELAY_VALUE_13_RP2_REG_P0_0,
+        MCA_DP16_WR_DELAY_VALUE_14_RP2_REG_P0_0,
+        MCA_DP16_WR_DELAY_VALUE_15_RP2_REG_P0_0,
+        MCA_DP16_WR_DELAY_VALUE_16_RP2_REG_P0_0,
+        MCA_DP16_WR_DELAY_VALUE_18_RP2_REG_P0_0,
+        MCA_DP16_WR_DELAY_VALUE_20_RP2_REG_P0_0,
+        MCA_DP16_WR_DELAY_VALUE_22_RP2_REG_P0_0,
+        // DP1
+        MCA_DP16_WR_DELAY_VALUE_0_RP2_REG_P0_1,
+        MCA_DP16_WR_DELAY_VALUE_1_RP2_REG_P0_1,
+        MCA_DP16_WR_DELAY_VALUE_2_RP2_REG_P0_1,
+        MCA_DP16_WR_DELAY_VALUE_3_RP2_REG_P0_1,
+        MCA_DP16_WR_DELAY_VALUE_4_RP2_REG_P0_1,
+        MCA_DP16_WR_DELAY_VALUE_5_RP2_REG_P0_1,
+        MCA_DP16_WR_DELAY_VALUE_6_RP2_REG_P0_1,
+        MCA_DP16_WR_DELAY_VALUE_7_RP2_REG_P0_1,
+        MCA_DP16_WR_DELAY_VALUE_8_RP2_REG_P0_1,
+        MCA_DP16_WR_DELAY_VALUE_9_RP2_REG_P0_1,
+        MCA_DP16_WR_DELAY_VALUE_10_RP2_REG_P0_1,
+        MCA_DP16_WR_DELAY_VALUE_11_RP2_REG_P0_1,
+        MCA_DP16_WR_DELAY_VALUE_12_RP2_REG_P0_1,
+        MCA_DP16_WR_DELAY_VALUE_13_RP2_REG_P0_1,
+        MCA_DP16_WR_DELAY_VALUE_14_RP2_REG_P0_1,
+        MCA_DP16_WR_DELAY_VALUE_15_RP2_REG_P0_1,
+        MCA_DP16_WR_DELAY_VALUE_16_RP2_REG_P0_1,
+        MCA_DP16_WR_DELAY_VALUE_18_RP2_REG_P0_1,
+        MCA_DP16_WR_DELAY_VALUE_20_RP2_REG_P0_1,
+        MCA_DP16_WR_DELAY_VALUE_22_RP2_REG_P0_1,
+        // DP2
+        MCA_DP16_WR_DELAY_VALUE_0_RP2_REG_P0_2,
+        MCA_DP16_WR_DELAY_VALUE_1_RP2_REG_P0_2,
+        MCA_DP16_WR_DELAY_VALUE_2_RP2_REG_P0_2,
+        MCA_DP16_WR_DELAY_VALUE_3_RP2_REG_P0_2,
+        MCA_DP16_WR_DELAY_VALUE_4_RP2_REG_P0_2,
+        MCA_DP16_WR_DELAY_VALUE_5_RP2_REG_P0_2,
+        MCA_DP16_WR_DELAY_VALUE_6_RP2_REG_P0_2,
+        MCA_DP16_WR_DELAY_VALUE_7_RP2_REG_P0_2,
+        MCA_DP16_WR_DELAY_VALUE_8_RP2_REG_P0_2,
+        MCA_DP16_WR_DELAY_VALUE_9_RP2_REG_P0_2,
+        MCA_DP16_WR_DELAY_VALUE_10_RP2_REG_P0_2,
+        MCA_DP16_WR_DELAY_VALUE_11_RP2_REG_P0_2,
+        MCA_DP16_WR_DELAY_VALUE_12_RP2_REG_P0_2,
+        MCA_DP16_WR_DELAY_VALUE_13_RP2_REG_P0_2,
+        MCA_DP16_WR_DELAY_VALUE_14_RP2_REG_P0_2,
+        MCA_DP16_WR_DELAY_VALUE_15_RP2_REG_P0_2,
+        MCA_DP16_WR_DELAY_VALUE_16_RP2_REG_P0_2,
+        MCA_DP16_WR_DELAY_VALUE_18_RP2_REG_P0_2,
+        MCA_DP16_WR_DELAY_VALUE_20_RP2_REG_P0_2,
+        MCA_DP16_WR_DELAY_VALUE_22_RP2_REG_P0_2,
+        // DP3
+        MCA_DP16_WR_DELAY_VALUE_0_RP2_REG_P0_3,
+        MCA_DP16_WR_DELAY_VALUE_1_RP2_REG_P0_3,
+        MCA_DP16_WR_DELAY_VALUE_2_RP2_REG_P0_3,
+        MCA_DP16_WR_DELAY_VALUE_3_RP2_REG_P0_3,
+        MCA_DP16_WR_DELAY_VALUE_4_RP2_REG_P0_3,
+        MCA_DP16_WR_DELAY_VALUE_5_RP2_REG_P0_3,
+        MCA_DP16_WR_DELAY_VALUE_6_RP2_REG_P0_3,
+        MCA_DP16_WR_DELAY_VALUE_7_RP2_REG_P0_3,
+        MCA_DP16_WR_DELAY_VALUE_8_RP2_REG_P0_3,
+        MCA_DP16_WR_DELAY_VALUE_9_RP2_REG_P0_3,
+        MCA_DP16_WR_DELAY_VALUE_10_RP2_REG_P0_3,
+        MCA_DP16_WR_DELAY_VALUE_11_RP2_REG_P0_3,
+        MCA_DP16_WR_DELAY_VALUE_12_RP2_REG_P0_3,
+        MCA_DP16_WR_DELAY_VALUE_13_RP2_REG_P0_3,
+        MCA_DP16_WR_DELAY_VALUE_14_RP2_REG_P0_3,
+        MCA_DP16_WR_DELAY_VALUE_15_RP2_REG_P0_3,
+        MCA_DP16_WR_DELAY_VALUE_16_RP2_REG_P0_3,
+        MCA_DP16_WR_DELAY_VALUE_18_RP2_REG_P0_3,
+        MCA_DP16_WR_DELAY_VALUE_20_RP2_REG_P0_3,
+        MCA_DP16_WR_DELAY_VALUE_22_RP2_REG_P0_3,
+        // DP4
+        MCA_DP16_WR_DELAY_VALUE_0_RP2_REG_P0_4,
+        MCA_DP16_WR_DELAY_VALUE_1_RP2_REG_P0_4,
+        MCA_DP16_WR_DELAY_VALUE_2_RP2_REG_P0_4,
+        MCA_DP16_WR_DELAY_VALUE_3_RP2_REG_P0_4,
+        MCA_DP16_WR_DELAY_VALUE_4_RP2_REG_P0_4,
+        MCA_DP16_WR_DELAY_VALUE_5_RP2_REG_P0_4,
+        MCA_DP16_WR_DELAY_VALUE_6_RP2_REG_P0_4,
+        MCA_DP16_WR_DELAY_VALUE_7_RP2_REG_P0_4,
+        MCA_DP16_WR_DELAY_VALUE_8_RP2_REG_P0_4,
+        MCA_DP16_WR_DELAY_VALUE_9_RP2_REG_P0_4,
+        MCA_DP16_WR_DELAY_VALUE_10_RP2_REG_P0_4,
+        MCA_DP16_WR_DELAY_VALUE_11_RP2_REG_P0_4,
+        MCA_DP16_WR_DELAY_VALUE_12_RP2_REG_P0_4,
+        MCA_DP16_WR_DELAY_VALUE_13_RP2_REG_P0_4,
+        MCA_DP16_WR_DELAY_VALUE_14_RP2_REG_P0_4,
+        MCA_DP16_WR_DELAY_VALUE_15_RP2_REG_P0_4,
+        MCA_DP16_WR_DELAY_VALUE_16_RP2_REG_P0_4,
+        MCA_DP16_WR_DELAY_VALUE_18_RP2_REG_P0_4,
+        MCA_DP16_WR_DELAY_VALUE_20_RP2_REG_P0_4,
+        MCA_DP16_WR_DELAY_VALUE_22_RP2_REG_P0_4,
+    },
+    // RP3
+    {
+        // DP0
+        MCA_DP16_WR_DELAY_VALUE_0_RP3_REG_P0_0,
+        MCA_DP16_WR_DELAY_VALUE_1_RP3_REG_P0_0,
+        MCA_DP16_WR_DELAY_VALUE_2_RP3_REG_P0_0,
+        MCA_DP16_WR_DELAY_VALUE_3_RP3_REG_P0_0,
+        MCA_DP16_WR_DELAY_VALUE_4_RP3_REG_P0_0,
+        MCA_DP16_WR_DELAY_VALUE_5_RP3_REG_P0_0,
+        MCA_DP16_WR_DELAY_VALUE_6_RP3_REG_P0_0,
+        MCA_DP16_WR_DELAY_VALUE_7_RP3_REG_P0_0,
+        MCA_DP16_WR_DELAY_VALUE_8_RP3_REG_P0_0,
+        MCA_DP16_WR_DELAY_VALUE_9_RP3_REG_P0_0,
+        MCA_DP16_WR_DELAY_VALUE_10_RP3_REG_P0_0,
+        MCA_DP16_WR_DELAY_VALUE_11_RP3_REG_P0_0,
+        MCA_DP16_WR_DELAY_VALUE_12_RP3_REG_P0_0,
+        MCA_DP16_WR_DELAY_VALUE_13_RP3_REG_P0_0,
+        MCA_DP16_WR_DELAY_VALUE_14_RP3_REG_P0_0,
+        MCA_DP16_WR_DELAY_VALUE_15_RP3_REG_P0_0,
+        MCA_DP16_WR_DELAY_VALUE_16_RP3_REG_P0_0,
+        MCA_DP16_WR_DELAY_VALUE_18_RP3_REG_P0_0,
+        MCA_DP16_WR_DELAY_VALUE_20_RP3_REG_P0_0,
+        MCA_DP16_WR_DELAY_VALUE_22_RP3_REG_P0_0,
+        // DP1
+        MCA_DP16_WR_DELAY_VALUE_0_RP3_REG_P0_1,
+        MCA_DP16_WR_DELAY_VALUE_1_RP3_REG_P0_1,
+        MCA_DP16_WR_DELAY_VALUE_2_RP3_REG_P0_1,
+        MCA_DP16_WR_DELAY_VALUE_3_RP3_REG_P0_1,
+        MCA_DP16_WR_DELAY_VALUE_4_RP3_REG_P0_1,
+        MCA_DP16_WR_DELAY_VALUE_5_RP3_REG_P0_1,
+        MCA_DP16_WR_DELAY_VALUE_6_RP3_REG_P0_1,
+        MCA_DP16_WR_DELAY_VALUE_7_RP3_REG_P0_1,
+        MCA_DP16_WR_DELAY_VALUE_8_RP3_REG_P0_1,
+        MCA_DP16_WR_DELAY_VALUE_9_RP3_REG_P0_1,
+        MCA_DP16_WR_DELAY_VALUE_10_RP3_REG_P0_1,
+        MCA_DP16_WR_DELAY_VALUE_11_RP3_REG_P0_1,
+        MCA_DP16_WR_DELAY_VALUE_12_RP3_REG_P0_1,
+        MCA_DP16_WR_DELAY_VALUE_13_RP3_REG_P0_1,
+        MCA_DP16_WR_DELAY_VALUE_14_RP3_REG_P0_1,
+        MCA_DP16_WR_DELAY_VALUE_15_RP3_REG_P0_1,
+        MCA_DP16_WR_DELAY_VALUE_16_RP3_REG_P0_1,
+        MCA_DP16_WR_DELAY_VALUE_18_RP3_REG_P0_1,
+        MCA_DP16_WR_DELAY_VALUE_20_RP3_REG_P0_1,
+        MCA_DP16_WR_DELAY_VALUE_22_RP3_REG_P0_1,
+        // DP2
+        MCA_DP16_WR_DELAY_VALUE_0_RP3_REG_P0_2,
+        MCA_DP16_WR_DELAY_VALUE_1_RP3_REG_P0_2,
+        MCA_DP16_WR_DELAY_VALUE_2_RP3_REG_P0_2,
+        MCA_DP16_WR_DELAY_VALUE_3_RP3_REG_P0_2,
+        MCA_DP16_WR_DELAY_VALUE_4_RP3_REG_P0_2,
+        MCA_DP16_WR_DELAY_VALUE_5_RP3_REG_P0_2,
+        MCA_DP16_WR_DELAY_VALUE_6_RP3_REG_P0_2,
+        MCA_DP16_WR_DELAY_VALUE_7_RP3_REG_P0_2,
+        MCA_DP16_WR_DELAY_VALUE_8_RP3_REG_P0_2,
+        MCA_DP16_WR_DELAY_VALUE_9_RP3_REG_P0_2,
+        MCA_DP16_WR_DELAY_VALUE_10_RP3_REG_P0_2,
+        MCA_DP16_WR_DELAY_VALUE_11_RP3_REG_P0_2,
+        MCA_DP16_WR_DELAY_VALUE_12_RP3_REG_P0_2,
+        MCA_DP16_WR_DELAY_VALUE_13_RP3_REG_P0_2,
+        MCA_DP16_WR_DELAY_VALUE_14_RP3_REG_P0_2,
+        MCA_DP16_WR_DELAY_VALUE_15_RP3_REG_P0_2,
+        MCA_DP16_WR_DELAY_VALUE_16_RP3_REG_P0_2,
+        MCA_DP16_WR_DELAY_VALUE_18_RP3_REG_P0_2,
+        MCA_DP16_WR_DELAY_VALUE_20_RP3_REG_P0_2,
+        MCA_DP16_WR_DELAY_VALUE_22_RP3_REG_P0_2,
+        // DP3
+        MCA_DP16_WR_DELAY_VALUE_0_RP3_REG_P0_3,
+        MCA_DP16_WR_DELAY_VALUE_1_RP3_REG_P0_3,
+        MCA_DP16_WR_DELAY_VALUE_2_RP3_REG_P0_3,
+        MCA_DP16_WR_DELAY_VALUE_3_RP3_REG_P0_3,
+        MCA_DP16_WR_DELAY_VALUE_4_RP3_REG_P0_3,
+        MCA_DP16_WR_DELAY_VALUE_5_RP3_REG_P0_3,
+        MCA_DP16_WR_DELAY_VALUE_6_RP3_REG_P0_3,
+        MCA_DP16_WR_DELAY_VALUE_7_RP3_REG_P0_3,
+        MCA_DP16_WR_DELAY_VALUE_8_RP3_REG_P0_3,
+        MCA_DP16_WR_DELAY_VALUE_9_RP3_REG_P0_3,
+        MCA_DP16_WR_DELAY_VALUE_10_RP3_REG_P0_3,
+        MCA_DP16_WR_DELAY_VALUE_11_RP3_REG_P0_3,
+        MCA_DP16_WR_DELAY_VALUE_12_RP3_REG_P0_3,
+        MCA_DP16_WR_DELAY_VALUE_13_RP3_REG_P0_3,
+        MCA_DP16_WR_DELAY_VALUE_14_RP3_REG_P0_3,
+        MCA_DP16_WR_DELAY_VALUE_15_RP3_REG_P0_3,
+        MCA_DP16_WR_DELAY_VALUE_16_RP3_REG_P0_3,
+        MCA_DP16_WR_DELAY_VALUE_18_RP3_REG_P0_3,
+        MCA_DP16_WR_DELAY_VALUE_20_RP3_REG_P0_3,
+        MCA_DP16_WR_DELAY_VALUE_22_RP3_REG_P0_3,
+        // DP4
+        MCA_DP16_WR_DELAY_VALUE_0_RP3_REG_P0_4,
+        MCA_DP16_WR_DELAY_VALUE_1_RP3_REG_P0_4,
+        MCA_DP16_WR_DELAY_VALUE_2_RP3_REG_P0_4,
+        MCA_DP16_WR_DELAY_VALUE_3_RP3_REG_P0_4,
+        MCA_DP16_WR_DELAY_VALUE_4_RP3_REG_P0_4,
+        MCA_DP16_WR_DELAY_VALUE_5_RP3_REG_P0_4,
+        MCA_DP16_WR_DELAY_VALUE_6_RP3_REG_P0_4,
+        MCA_DP16_WR_DELAY_VALUE_7_RP3_REG_P0_4,
+        MCA_DP16_WR_DELAY_VALUE_8_RP3_REG_P0_4,
+        MCA_DP16_WR_DELAY_VALUE_9_RP3_REG_P0_4,
+        MCA_DP16_WR_DELAY_VALUE_10_RP3_REG_P0_4,
+        MCA_DP16_WR_DELAY_VALUE_11_RP3_REG_P0_4,
+        MCA_DP16_WR_DELAY_VALUE_12_RP3_REG_P0_4,
+        MCA_DP16_WR_DELAY_VALUE_13_RP3_REG_P0_4,
+        MCA_DP16_WR_DELAY_VALUE_14_RP3_REG_P0_4,
+        MCA_DP16_WR_DELAY_VALUE_15_RP3_REG_P0_4,
+        MCA_DP16_WR_DELAY_VALUE_16_RP3_REG_P0_4,
+        MCA_DP16_WR_DELAY_VALUE_18_RP3_REG_P0_4,
+        MCA_DP16_WR_DELAY_VALUE_20_RP3_REG_P0_4,
+        MCA_DP16_WR_DELAY_VALUE_22_RP3_REG_P0_4,
+    },
+};
+
 ///
 /// @brief Given a RD_VREF value, create a PHY 'standard' bit field for that percentage.
 /// @tparam T fapi2 Target Type - derived
@@ -1759,7 +2195,7 @@ fapi_try_exit:
 /// @return FAPI2_RC_SUCCES iff ok
 ///
 template<>
-fapi2::ReturnCode rd_ctr_settings<TARGET_TYPE_MCA>::restore()
+fapi2::ReturnCode rd_ctr_settings<TARGET_TYPE_MCA>::restore() const
 {
     typedef mss::dp16Traits<TARGET_TYPE_MCA> TT;
 
@@ -1854,6 +2290,86 @@ fapi_try_exit:
 }
 
 ///
+/// @brief Save settings for a given rank pair
+/// @return FAPI2_RC_SUCCES iff ok
+///
+template<>
+fapi2::ReturnCode wr_ctr_settings<TARGET_TYPE_MCA>::save()
+{
+    typedef mss::dp16Traits<TARGET_TYPE_MCA> TT;
+
+    // Read each register and save in private variables
+    FAPI_TRY( mss::scom_suckah(iv_target, TT::WR_DELAY_REG[iv_rp], iv_write_delay) );
+    FAPI_TRY( mss::scom_suckah(iv_target, TT::BIT_DISABLE_REG[iv_rp], iv_dq_disable) );
+
+fapi_try_exit:
+    return fapi2::current_err;
+}
+
+///
+/// @brief Restore settings for a given rank pair
+/// @return FAPI2_RC_SUCCES iff ok
+///
+template<>
+fapi2::ReturnCode wr_ctr_settings<TARGET_TYPE_MCA>::restore() const
+{
+    typedef mss::dp16Traits<TARGET_TYPE_MCA> TT;
+
+    std::vector<fapi2::buffer<uint64_t>> l_post_training_settings;
+    std::vector<std::pair<fapi2::buffer<uint64_t>, fapi2::buffer<uint64_t> > > l_post_training_disables;
+
+    // Log values before restoring them
+    FAPI_TRY( mss::scom_suckah(iv_target, TT::WR_DELAY_REG[iv_rp], l_post_training_settings) );
+
+    if( l_post_training_settings.size() != iv_write_delay.size() )
+    {
+        // Asserting out instead of collecting FFDC since this is a
+        // programming bug that shouldn't occur.
+        FAPI_ERR("Number of WRITE_DELAY registers != number of stored registers: %d != %d",
+                 l_post_training_settings.size(), iv_write_delay.size());
+        fapi2::Assert(false);
+    }
+
+    // TK Should these messages be written in FFDC so we can see them in FW?
+    for (uint64_t l_idx = 0; l_idx < l_post_training_settings.size(); ++l_idx)
+    {
+        FAPI_INF("%s restoring value of WRITE_DELAY scom 0x%016llx from 0x%016llx to 0x%016llx",
+                 mss::c_str(iv_target), TT::WR_DELAY_REG[iv_rp][l_idx], l_post_training_settings[l_idx], iv_write_delay[l_idx]);
+    }
+
+    FAPI_TRY( mss::scom_suckah(iv_target, TT::BIT_DISABLE_REG[iv_rp], l_post_training_disables) );
+
+    if( l_post_training_disables.size() != iv_dq_disable.size() )
+    {
+        // Asserting out instead of collecting FFDC since this is a
+        // programming bug that shouldn't occur.
+        FAPI_ERR("Number of BIT_DISABLE registers != number of stored registers: %d != %d",
+                 l_post_training_disables.size(), iv_dq_disable.size());
+        fapi2::Assert(false);
+    }
+
+    for (uint64_t l_idx = 0; l_idx < l_post_training_disables.size(); ++l_idx)
+    {
+        FAPI_INF("%s restoring value of DATA_DISABLE scom 0x%016llx from 0x%016llx to 0x%016llx",
+                 mss::c_str(iv_target), TT::BIT_DISABLE_REG[iv_rp][l_idx].first, l_post_training_disables[l_idx].first,
+                 iv_dq_disable[l_idx].first);
+        FAPI_INF("%s restoring value of DATA_DISABLE scom 0x%016llx from 0x%016llx to 0x%016llx",
+                 mss::c_str(iv_target), TT::BIT_DISABLE_REG[iv_rp][l_idx].second, l_post_training_disables[l_idx].second,
+                 iv_dq_disable[l_idx].second);
+    }
+
+    // Write each register back from private variables
+    FAPI_TRY( mss::scom_blastah(iv_target, TT::WR_DELAY_REG[iv_rp], iv_write_delay) );
+    FAPI_TRY( mss::scom_blastah(iv_target, TT::BIT_DISABLE_REG[iv_rp], iv_dq_disable) );
+
+    // Run the record_bad_bits function to restore the BAD_DQ_BITMAP attribute using the pre-training disable bits
+    FAPI_TRY( mss::dp16::record_bad_bits(iv_target) );
+
+fapi_try_exit:
+    return fapi2::current_err;
+}
+
+///
 /// @brief Reset the data bit enable registers
 /// @param[in] i_target  a port target
 /// @return FAPI2_RC_SUCCES iff ok
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/phy/dp16.H b/src/import/chips/p9/procedures/hwp/memory/lib/phy/dp16.H
index e36b5969a..40924bc20 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/phy/dp16.H
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/phy/dp16.H
@@ -184,6 +184,9 @@ class dp16Traits<fapi2::TARGET_TYPE_MCA>
 
         static const std::vector<std::vector<std::pair<uint64_t, uint64_t>>> BIT_DISABLE_REG;
 
+        // WR delay register
+        static const std::vector<std::vector<uint64_t>> WR_DELAY_REG;
+
         // WR VREF registers
         static const std::vector< uint64_t > WR_VREF_CONFIG0_REG;
         static const std::vector< uint64_t > WR_VREF_CONFIG1_REG;
@@ -452,7 +455,7 @@ class rd_ctr_settings
         /// @brief Restore settings for a given rank pair
         /// @return FAPI2_RC_SUCCES iff ok
         ///
-        fapi2::ReturnCode restore();
+        fapi2::ReturnCode restore() const;
 
     private:
         const fapi2::Target<T> iv_target;
@@ -464,6 +467,46 @@ class rd_ctr_settings
 };
 
 ///
+/// @class wr_ctr_settings
+/// @brief Stores pre-training_adv WR_CTR PHY settings, so they can be restored if training_adv fails
+/// @tparam T target type representing a port
+///
+template< fapi2::TargetType T >
+class wr_ctr_settings
+{
+    public:
+        wr_ctr_settings() = delete;
+
+        ///
+        /// @brief rd_ctr_settings constructor
+        /// @param[in] i_target the port target
+        /// @param[in] i_rp the rank pair
+        ///
+        wr_ctr_settings( const fapi2::Target<T>& i_target, const uint64_t i_rp ):
+            iv_target(i_target), iv_rp(i_rp)
+        {
+        }
+
+        ///
+        /// @brief Save settings for a given rank pair
+        /// @return FAPI2_RC_SUCCES iff ok
+        ///
+        fapi2::ReturnCode save();
+
+        ///
+        /// @brief Restore settings for a given rank pair
+        /// @return FAPI2_RC_SUCCES iff ok
+        ///
+        fapi2::ReturnCode restore() const;
+
+    private:
+        const fapi2::Target<T> iv_target;
+        const uint64_t iv_rp;
+        std::vector<fapi2::buffer<uint64_t>> iv_write_delay;
+        std::vector<std::pair<fapi2::buffer<uint64_t>, fapi2::buffer<uint64_t> > > iv_dq_disable;
+};
+
+///
 /// @brief Read TSYS_DATA
 /// @tparam I DP16 instance
 /// @tparam T fapi2 Target Type - derived
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/phy/mss_training.C b/src/import/chips/p9/procedures/hwp/memory/lib/phy/mss_training.C
index 6f0ba4e72..e8ee65ad8 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/phy/mss_training.C
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/phy/mss_training.C
@@ -55,6 +55,7 @@
 #include <lib/dimm/rank.H>
 #include <lib/shared/mss_const.H>
 #include <lib/dimm/ddr4/pda.H>
+#include <lib/phy/seq.H>
 
 namespace mss
 {
@@ -222,6 +223,7 @@ uint64_t wr_lvl::calculate_cycles( const fapi2::Target<fapi2::TARGET_TYPE_MCA>&
 {
     const uint64_t TWLO_TWLOE = mss::twlo_twloe(i_target);
 
+    // Note: the following equation is taken from the PHY workbook - leaving the naked numbers in for parity to the workbook
     // This step runs for approximately (80 + TWLO_TWLOE) x NUM_VALID_SAMPLES x (384/(BIG_STEP + 1) +
     // (2 x (BIG_STEP + 1))/(SMALL_STEP + 1)) + 20 memory clock cycles per rank.
 
@@ -313,6 +315,7 @@ fapi_try_exit:
 ///
 uint64_t dqs_align::calculate_cycles( const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target ) const
 {
+    // Note: the following equation is taken from the PHY workbook - leaving the naked numbers in for parity to the workbook
     // This step runs for approximately 6 x 600 x 4 DRAM clocks per rank pair.
     const uint64_t l_dqs_align_cycles = 6 * 600 * 4;
 
@@ -369,6 +372,7 @@ fapi_try_exit:
 ///
 uint64_t rdclk_align::calculate_cycles( const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target ) const
 {
+    // Note: the following equation is taken from the PHY workbook - leaving the naked numbers in for parity to the workbook
     // This step runs for approximately 24 x ((1024/COARSE_CAL_STEP_SIZE + 4 x COARSE_CAL_STEP_SIZE) x 4 + 32) DRAM
     // clocks per rank pair
     const uint64_t l_rdclk_align_cycles = 24 * ((1024 / COARSE_CAL_STEP_SIZE + 4 * COARSE_CAL_STEP_SIZE) * 4 + 32);
@@ -469,6 +473,7 @@ fapi_try_exit:
 ///
 uint64_t read_ctr::calculate_cycles( const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target ) const
 {
+    // Note: the following equation is taken from the PHY workbook - leaving the naked numbers in for parity to the workbook
     // This step runs for approximately 6 x (512/COARSE_CAL_STEP_SIZE + 4 x (COARSE_CAL_STEP_SIZE +
     // 4 x CONSEQ_PASS)) x 24 DRAM clocks per rank pair.
 
@@ -749,6 +754,7 @@ fapi_try_exit:
 ///
 uint64_t write_ctr::calculate_cycles( const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target ) const
 {
+    // Note: the following equation is taken from the PHY workbook - leaving the naked numbers in for parity to the workbook
     // 1000 + (NUM_VALID_SAMPLES * (FW_WR_RD + FW_RD_WR + 16) *
     // (1024/(SMALL_STEP +1) + 128/(BIG_STEP +1)) + 2 * (BIG_STEP+1)/(SMALL_STEP+1)) x 24 DRAM
     // clocks per rank pair.
@@ -790,6 +796,7 @@ fapi_try_exit:
 ///
 uint64_t coarse_wr_rd::calculate_cycles( const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target ) const
 {
+    // Note: the following equation is taken from the PHY workbook - leaving the naked numbers in for parity to the workbook
     // The run length given here is the maximum run length for this calibration algorithm.
     // This step runs for approximately 40 DRAM clocks per rank pair.
     constexpr uint64_t COARSE_WR_CYCLES = 40;
@@ -824,13 +831,101 @@ fapi2::ReturnCode custom_read_ctr::pre_workaround( const fapi2::Target<fapi2::TA
         const uint8_t i_abort_on_error ) const
 {
     FAPI_DBG("%s Running Pre-Custom RD CTR workaround steps on RP%d", mss::c_str(i_target), i_rp);
-    // Turn off refresh
+
+    // Sets up the patterns to run
+    // Note: not technically a workaround
+    {
+        // Let's set the pattern to run
+        FAPI_TRY( mss::configure_custom_pattern(i_target) );
+
+        // Set staggered mode
+        FAPI_TRY( mss::rc::change_staggered_pattern(i_target) );
+
+        // Set custom read centering mode
+        FAPI_TRY( mss::dp16::setup_custom_read_centering_mode(i_target), "Error in p9_mss_draminit_training %s",
+                  mss::c_str(i_target) );
+    }
+
+    // Runs initial pattern write
+    {
+        const auto l_ipw = std::make_shared<initial_pattern_write>();
+
+        // Executes initial pattern write
+        FAPI_TRY(l_ipw->execute(i_target, i_rp, i_abort_on_error), "%s failed to execute IPW", mss::c_str(i_target));
+    }
+
+    // Turn off refresh - this is an actual workaround
     FAPI_TRY( mss::workarounds::dqs_align::turn_off_refresh(i_target) );
 fapi_try_exit:
     return fapi2::current_err;
 }
 
 ///
+/// @brief Runs the backup pattern if need be
+/// @param[in] i_target - the MCA target on which to operate
+/// @param[in] i_rp - the rank pair
+/// @param[in] i_abort_on_error - whether or not we are aborting on cal error
+/// @param[in] i_fails_on_rp - the fails taken from training advanced
+/// @param[in] i_original_settings - the settings to restore if we take a failure on the backup patterns
+/// @return fapi2::ReturnCode fapi2::FAPI2_RC_SUCCESS iff ok
+///
+fapi2::ReturnCode custom_read_ctr::backup_pattern_run( const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target,
+        const uint64_t i_rp,
+        const uint8_t i_abort_on_error,
+        const std::vector<fapi2::ReturnCode>& i_fails_on_rp,
+        const mss::dp16::rd_ctr_settings<fapi2::TARGET_TYPE_MCA>& i_original_settings ) const
+{
+    // If we got a fail, let's ignore the previous fails and run backup pattern
+    if (i_fails_on_rp.size() != 0)
+    {
+        std::vector<fapi2::ReturnCode> l_fails_on_rp;
+        bool l_cal_fail = false;
+        fapi2::buffer<uint32_t> l_backup;
+
+        // Clear the disable bits from last run.
+        // This function restores bad_bits to how the attribute has them
+        // (which was updated at the end of regular training)
+        // So we won't run on known bad bits, but will rerun on the iffy bits from last custom_pattern run
+        FAPI_TRY( mss::dp16::reset_bad_bits(i_target) );
+        FAPI_INF("%s rp%x running back up pattern for draminit_training_adv", mss::c_str(i_target), i_rp);
+
+        // Clear the cal errors so we can retry
+        FAPI_TRY( mss::clear_initial_cal_errors(i_target), "%s error resetting errors prior to init cal", mss::c_str(i_target));
+
+        FAPI_TRY( mss::custom_training_adv_backup_patterns(i_target, l_backup) );
+
+        // Put the backup into the registers
+        FAPI_TRY( mss::seq::setup_rd_wr_data(i_target, l_backup) );
+
+        // Runs initial pattern write
+        {
+            const auto l_ipw = std::make_shared<initial_pattern_write>();
+
+            // Executes initial pattern write
+            FAPI_TRY( l_ipw->execute(i_target, i_rp, i_abort_on_error), "%s failed to re-execute IPW", mss::c_str(i_target));
+        }
+
+        // Rerun the training for this rp
+        FAPI_TRY( phy_step::run(i_target, i_rp, i_abort_on_error), "%s failed re-running CUSTOM_RD_CTR", mss::c_str(i_target));
+
+        FAPI_TRY( mss::find_and_log_cal_errors(i_target, i_rp, i_abort_on_error, l_cal_fail, l_fails_on_rp) );
+
+        // If we got fails from the backup pattern, restore the pre-adv training settings for this rank pair
+        if (l_fails_on_rp.size() != 0)
+        {
+            l_fails_on_rp.clear();
+            FAPI_INF("%s rp%d draminit_training_adv failed. Restoring original settings", mss::c_str(i_target), i_rp);
+
+            // Restore pre-training_adv settings
+            FAPI_TRY( i_original_settings.restore() );
+        }
+    }
+
+fapi_try_exit:
+    return fapi2::current_err;
+}
+
+///
 /// @brief Executes a cal step with workarounds
 /// @param[in] i_target - the MCA target on which to operate
 /// @param[in] i_rp - the rank pair
@@ -843,11 +938,28 @@ fapi2::ReturnCode custom_read_ctr::run( const fapi2::Target<fapi2::TARGET_TYPE_M
 {
     constexpr bool RUN_RD_CTR = true;
     constexpr bool SKIP_RD_VREF = false;
+
+    std::vector<fapi2::ReturnCode> l_fails_on_rp;
+    bool l_cal_fail = false;
+
+    // Save off registers in case adv training fails
+    mss::dp16::rd_ctr_settings<fapi2::TARGET_TYPE_MCA> l_original_settings(i_target, i_rp);
+
+    // Setup the initial settings
+    FAPI_TRY( l_original_settings.save() );
+
+    // Clear all of the errors before we start
+    FAPI_TRY(mss::clear_initial_cal_errors(i_target), "%s error resetting errors prior to init cal", mss::c_str(i_target));
+
     // Now lets set the actual read_vref_config. We want to write/ clear this every time we run so seperate function
     FAPI_TRY( setup_read_vref_config1(i_target, RUN_RD_CTR, SKIP_RD_VREF),
               "%s Failed setting the read_vref_config1", mss::c_str(i_target) );
 
-    FAPI_TRY(phy_step::run(i_target, i_rp, i_abort_on_error));
+    FAPI_TRY( phy_step::run(i_target, i_rp, i_abort_on_error) );
+
+    // Runs the backup pattern if we took a fail here
+    FAPI_TRY( mss::find_and_log_cal_errors(i_target, i_rp, i_abort_on_error, l_cal_fail, l_fails_on_rp) );
+    FAPI_TRY( backup_pattern_run( i_target, i_rp, i_abort_on_error, l_fails_on_rp, l_original_settings ));
 
 fapi_try_exit:
     return fapi2::current_err;
@@ -865,6 +977,7 @@ fapi2::ReturnCode custom_read_ctr::post_workaround( const fapi2::Target<fapi2::T
         const uint8_t i_abort_on_error ) const
 {
     FAPI_DBG("%s Running Post-Custom RD CTR workaround steps on RP%d", mss::c_str(i_target), i_rp);
+
     // Turn refresh back on
     FAPI_TRY( mss::workarounds::dqs_align::turn_on_refresh(i_target) );
 
@@ -879,6 +992,7 @@ fapi_try_exit:
 ///
 uint64_t custom_read_ctr::calculate_cycles( const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target ) const
 {
+    // Note: the following equation is taken from the PHY workbook - leaving the naked numbers in for parity to the workbook
     // This step runs for approximately 6 x (512/COARSE_CAL_STEP_SIZE + 4 x (COARSE_CAL_STEP_SIZE +
     // 4 x CONSEQ_PASS)) x 24 DRAM clocks per rank pair.
 
@@ -895,6 +1009,104 @@ uint64_t custom_read_ctr::calculate_cycles( const fapi2::Target<fapi2::TARGET_TY
 }
 
 ///
+/// @brief Executes a cal step with workarounds
+/// @param[in] i_target - the MCA target on which to operate
+/// @param[in] i_rp - the rank pair
+/// @param[in] i_abort_on_error - whether or not we are aborting on cal error
+/// @return fapi2::ReturnCode fapi2::FAPI2_RC_SUCCESS iff ok
+///
+fapi2::ReturnCode custom_write_ctr::run( const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target,
+        const uint64_t i_rp,
+        const uint8_t i_abort_on_error ) const
+{
+    typedef mss::dp16Traits<fapi2::TARGET_TYPE_MCA> TT;
+    std::vector<fapi2::buffer<uint64_t>> l_wr_vref_config;
+    std::vector<fapi2::ReturnCode> l_fails_on_rp;
+    bool l_cal_fail = false;
+
+    // Save off registers in case adv training fails
+    mss::dp16::wr_ctr_settings<fapi2::TARGET_TYPE_MCA> l_original_settings(i_target, i_rp);
+
+    // Setup the initial settings
+    FAPI_TRY( l_original_settings.save() );
+
+    // Configure the WR config to only run the 1D algorithm
+    FAPI_TRY( mss::scom_suckah(i_target, TT::WR_VREF_CONFIG0_REG, l_wr_vref_config) );
+
+    // Loops ensures that only the 1D algorithm will run
+    for(auto& l_data : l_wr_vref_config)
+    {
+        // 1: Run only the 1D
+        l_data.setBit<TT::WR_VREF_CONFIG0_1D_ONLY_SWITCH>();
+    }
+
+    FAPI_TRY(mss::scom_blastah(i_target, TT::WR_VREF_CONFIG0_REG, l_wr_vref_config));
+
+    // Let's set the pattern to run
+    FAPI_TRY( mss::configure_custom_wr_pattern(i_target) );
+
+    // Set staggered mode
+    FAPI_TRY( mss::rc::change_staggered_pattern(i_target) );
+
+    FAPI_TRY( phy_step::run(i_target, i_rp, i_abort_on_error) );
+    FAPI_TRY( mss::find_and_log_cal_errors(i_target, i_rp, i_abort_on_error, l_cal_fail, l_fails_on_rp) );
+
+    // If we took a fail, restore those settings
+    if(!l_fails_on_rp.empty())
+    {
+        // TK yes, this shouldn't be here, but for now we need a way to note that we took an error.  We'll add in FFDC later on to fix this
+        // We'll want it to be informational to note "Hey, I saw an error here but could recover" we'll want the same thing in custom RD
+        FAPI_ERR("%s RP%lu took a fail in CUSTOM_WRITE_CTR!", mss::c_str(i_target), i_rp);
+        FAPI_TRY( l_original_settings.restore() );
+    }
+
+fapi_try_exit:
+    return fapi2::current_err;
+}
+
+///
+/// @brief Calculates the number of cycles a given calibration step will take
+/// @param[in] i_target - the MCA target on which to operate
+/// @return l_cycles - the number of cycles a given calibration step wil take
+///
+uint64_t custom_write_ctr::calculate_cycles( const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target ) const
+{
+    // Note: the following equation is taken from the PHY workbook - leaving the naked numbers in for parity to the workbook
+    // 1000 + (NUM_VALID_SAMPLES * (FW_WR_RD + FW_RD_WR + 16) *
+    // (1024/(SMALL_STEP +1) + 128/(BIG_STEP +1)) + 2 * (BIG_STEP+1)/(SMALL_STEP+1)) x 24 DRAM
+    // clocks per rank pair.
+    constexpr uint64_t WR_CNTR_FW_WR_RD = mss::fw_wr_rd();
+    uint8_t l_fw_rd_wr = 0;
+    uint64_t l_cycles = 1;
+
+    FAPI_TRY( mss::fw_rd_wr(i_target, l_fw_rd_wr) );
+
+    l_cycles = 1000 + (WR_LVL_NUM_VALID_SAMPLES * (WR_CNTR_FW_WR_RD + l_fw_rd_wr + 16) *
+                       (1024 / (WR_LVL_SMALL_STEP + 1) + 128 / (WR_LVL_BIG_STEP + 1)) + 2 *
+                       (WR_LVL_BIG_STEP + 1) / (WR_LVL_SMALL_STEP + 1)) * 24;
+
+    FAPI_DBG("%s write_ctr_cycles: %lu(%luns) (%u, %u, %u, %u, %u)",
+             mss::c_str(i_target),
+             l_cycles,
+             mss::cycles_to_ns(i_target, l_cycles),
+             WR_LVL_NUM_VALID_SAMPLES,
+             WR_CNTR_FW_WR_RD,
+             l_fw_rd_wr,
+             WR_LVL_BIG_STEP,
+             WR_LVL_SMALL_STEP);
+
+    return l_cycles;
+
+fapi_try_exit:
+    // We had an error, let's exit
+    FAPI_ERR("%s had an error and is going to exit", mss::c_str(i_target));
+    fapi2::Assert(false);
+
+    // Error case, the return is to make the compiler happy
+    return l_cycles;
+}
+
+///
 /// @brief Creates the vector of training steps to loop over
 /// @param[in] i_cal_steps - the bit mask of calibration steps
 /// @param[in] i_sim - simulation mode or not
@@ -980,13 +1192,20 @@ std::vector<std::shared_ptr<step>> steps_factory(const fapi2::buffer<uint32_t>&
         l_steps.push_back(std::make_shared<coarse_wr_rd>());
     }
 
-    // Training Advanced - aka custom pattern RD CTR
-    if(i_cal_steps.getBit<mss::cal_steps::TRAINING_ADV>())
+    // Training Advanced Read - aka custom pattern RD CTR
+    if(i_cal_steps.getBit<mss::cal_steps::TRAINING_ADV_RD>())
     {
         FAPI_INF("Custom RD_CTR is enabled");
         l_steps.push_back(std::make_shared<custom_read_ctr>());
     }
 
+    // Training Advanced Write - aka custom pattern WR CTR
+    if(i_cal_steps.getBit<mss::cal_steps::TRAINING_ADV_WR>())
+    {
+        FAPI_INF("Custom WR_CTR is enabled");
+        l_steps.push_back(std::make_shared<custom_write_ctr>());
+    }
+
     return l_steps;
 }
 
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/phy/mss_training.H b/src/import/chips/p9/procedures/hwp/memory/lib/phy/mss_training.H
index 3ae5e3365..d8f8775ee 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/phy/mss_training.H
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/phy/mss_training.H
@@ -567,7 +567,7 @@ class write_ctr : public phy_step
         ///
         write_ctr(const bool i_wr_vref) :
             phy_step( fapi2::buffer<uint64_t>().setBit<MCA_DDRPHY_PC_INIT_CAL_CONFIG0_P0_ENA_WRITE_CTR>(),
-                      "write_ctr"),
+                      "WRITE_CTR"),
             iv_wr_vref(i_wr_vref)
         {}
 
@@ -728,6 +728,59 @@ class custom_read_ctr : public phy_step
                                            const uint8_t i_abort_on_error ) const override;
 
         ///
+        /// @brief Runs the backup pattern if need be
+        /// @param[in] i_target - the MCA target on which to operate
+        /// @param[in] i_rp - the rank pair
+        /// @param[in] i_abort_on_error - whether or not we are aborting on cal error
+        /// @param[in] i_fails_on_rp - the fails taken from training advanced
+        /// @param[in] i_original_settings - the settings to restore if we take a failure on the backup patterns
+        /// @return fapi2::ReturnCode fapi2::FAPI2_RC_SUCCESS iff ok
+        ///
+        fapi2::ReturnCode backup_pattern_run( const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target,
+                                              const uint64_t i_rp,
+                                              const uint8_t i_abort_on_error,
+                                              const std::vector<fapi2::ReturnCode>& i_fails_on_rp,
+                                              const mss::dp16::rd_ctr_settings<fapi2::TARGET_TYPE_MCA>& i_original_settings ) const;
+
+        ///
+        /// @brief Calculates the number of cycles a given calibration step will take
+        /// @param[in] i_target - the MCA target on which to operate
+        /// @return l_cycles - the number of cycles a given calibration step wil take
+        ///
+        uint64_t calculate_cycles( const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target ) const override;
+};
+
+///
+/// @brief Custom read centering - can include initial pattern write
+///
+class custom_write_ctr : public phy_step
+{
+    public:
+        ///
+        /// @brief Base constructor
+        ///
+        custom_write_ctr() :
+            phy_step( fapi2::buffer<uint64_t>().setBit<MCA_DDRPHY_PC_INIT_CAL_CONFIG0_P0_ENA_CUSTOM_WR>(),
+                      "CUSTOM_WRITE_CTR")
+        {}
+
+        ///
+        /// @brief Default destructor
+        ///
+        ~custom_write_ctr() override = default;
+
+        ///
+        /// @brief Sets up and runs the calibration step
+        /// @param[in] i_target - the MCA target on which to operate
+        /// @param[in] i_rp - the rank pair
+        /// @param[in] i_abort_on_error - whether or not we are aborting on cal error
+        /// @return fapi2::ReturnCode fapi2::FAPI2_RC_SUCCESS iff ok
+        ///
+        fapi2::ReturnCode run( const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target,
+                               const uint64_t i_rp,
+                               const uint8_t i_abort_on_error ) const override;
+
+        ///
         /// @brief Calculates the number of cycles a given calibration step will take
         /// @param[in] i_target - the MCA target on which to operate
         /// @return l_cycles - the number of cycles a given calibration step wil take
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/shared/mss_const.H b/src/import/chips/p9/procedures/hwp/memory/lib/shared/mss_const.H
index 4aa8db4cf..1958501e3 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/shared/mss_const.H
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/shared/mss_const.H
@@ -251,11 +251,12 @@ enum cal_steps : uint64_t
     WRITE_CTR         = 17, ///< Write Centering
     COARSE_WR         = 18, ///< Initial Coarse Pattern Write
     COARSE_RD         = 19, ///< Coarse Read Centering
-    TRAINING_ADV      = 20, ///< Flag for draminit training advance in the attribute/ CUSTOM_READ_CTR in code
+    TRAINING_ADV_RD   = 20, ///< Flag for draminit training advance in the attribute/ CUSTOM_READ_CTR in code
+    TRAINING_ADV_WR   = 21, ///< Flag for draminit training advance in the attribute/ CUSTOM_WRITE_CTR in code
 
     // Not *exactly* a cal step but go w/it
-    RUN_ALL_CAL_STEPS          = 0xFFFFF800,
-    RUN_CAL_SKIP_WR_RD_2D_VREF = 0xFFFD7800,
+    RUN_ALL_CAL_STEPS          = 0xFFFFFC00,
+    RUN_CAL_SKIP_WR_RD_2D_VREF = 0xFFFD7C00,
 
     INITIAL_PAT_WR_TO_RD_CTR_LEN = inclusive_range(INITIAL_PAT_WR, READ_CTR),
     WR_VREF_TO_COARSE_RD_LEN = inclusive_range(WRITE_CTR_2D_VREF, COARSE_RD),
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/workarounds/dqs_align_workarounds.C b/src/import/chips/p9/procedures/hwp/memory/lib/workarounds/dqs_align_workarounds.C
index 123329307..1839d103c 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/workarounds/dqs_align_workarounds.C
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/workarounds/dqs_align_workarounds.C
@@ -5,7 +5,7 @@
 /*                                                                        */
 /* OpenPOWER HostBoot Project                                             */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2017                             */
+/* Contributors Listed Below - COPYRIGHT 2017,2018                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
 /*                                                                        */
@@ -81,7 +81,7 @@ fapi2::ReturnCode set_init_cal_refresh(const fapi2::Target<fapi2::TARGET_TYPE_MC
     mss::pc::set_snoop_dis(l_data, mss::LOW);
     mss::pc::set_refresh_interval(l_data, REF_INTERVAL);
 
-    FAPI_TRY( mss::pc::write_init_cal_config1(i_target, l_data) )
+    FAPI_TRY( mss::pc::write_init_cal_config1(i_target, l_data) );
 
 fapi_try_exit:
     return fapi2::current_err;
@@ -102,7 +102,7 @@ fapi2::ReturnCode clear_init_cal_refresh(const fapi2::Target<fapi2::TARGET_TYPE_
 
     mss::pc::set_refresh_control(l_data, REF_CNTL);
 
-    FAPI_TRY( mss::pc::write_init_cal_config1(i_target, l_data) )
+    FAPI_TRY( mss::pc::write_init_cal_config1(i_target, l_data) );
 
 fapi_try_exit:
     return fapi2::current_err;
diff --git a/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit_training.C b/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit_training.C
index d16f2c1ee..ba15a905d 100644
--- a/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit_training.C
+++ b/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit_training.C
@@ -5,7 +5,7 @@
 /*                                                                        */
 /* OpenPOWER HostBoot Project                                             */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2015,2017                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2018                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
 /*                                                                        */
@@ -128,7 +128,7 @@ extern "C"
             }
 
             // Clear the Training Advance bit because this is used in training_adv and not in training
-            l_cal_steps_enabled.clearBit<mss::TRAINING_ADV>();
+            l_cal_steps_enabled.clearBit<mss::TRAINING_ADV_RD>().clearBit<mss::TRAINING_ADV_WR>();
 
             FAPI_DBG("cal steps enabled: 0x%x special training: 0x%x", l_cal_steps_enabled, i_special_training);
 
diff --git a/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit_training_adv.C b/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit_training_adv.C
index 4c46b2590..8c3af9240 100644
--- a/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit_training_adv.C
+++ b/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit_training_adv.C
@@ -5,7 +5,7 @@
 /*                                                                        */
 /* OpenPOWER HostBoot Project                                             */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2017                             */
+/* Contributors Listed Below - COPYRIGHT 2017,2018                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
 /*                                                                        */
@@ -92,18 +92,15 @@ extern "C"
             std::vector<std::shared_ptr<mss::training::step>> l_steps;
             FAPI_TRY( mss::cal_step_enable(p, l_cal_steps_enabled), "Error in p9_mss_draminit_training %s", mss::c_str(i_target) );
 
-            if (!l_cal_steps_enabled.getBit<mss::TRAINING_ADV>())
+            if (!((l_cal_steps_enabled.getBit<mss::TRAINING_ADV_RD>()) || (l_cal_steps_enabled.getBit<mss::TRAINING_ADV_WR>())))
             {
                 FAPI_INF("ATTR_MSS_CAL_STEPS_ENABLED says to skip draminit training advance, so skipping %s",
                          mss::c_str(i_target));
                 continue;
             }
 
-            // If we see the bit to for training_adv, let's set up our cal config.
-            // As per the PHY spec, only INITIAL_PAT_WRITE and the CUSTOM_RD_PATTERN bits should be set
-            // TRAINING_ADV == CUSTOM_RD_PATTERN
-            l_cal_steps_enabled = 0;
-            l_cal_steps_enabled.setBit<mss::INITIAL_PAT_WR>().setBit<mss::TRAINING_ADV>();
+            // Clear all non training advanced bits
+            l_cal_steps_enabled.clearBit<0, mss::TRAINING_ADV_RD>();
 
             // Gets the training steps to calibrate
             l_steps = mss::training::steps_factory(l_cal_steps_enabled, l_sim);
@@ -111,23 +108,10 @@ extern "C"
             // Keep track of the last error seen by a rank pair
             fapi2::ReturnCode l_rank_pair_error(fapi2::FAPI2_RC_SUCCESS);
 
-            // Clear all of the errors before we start
-            FAPI_TRY(mss::clear_initial_cal_errors(p), "%s error resetting errors prior to init cal", mss::c_str(p));
-
             // Returned from set_rank_pairs, it tells us how many rank pairs
             // we configured on this port.
             std::vector<uint64_t> l_pairs;
 
-            // Let's set the pattern to run
-            FAPI_TRY( mss::configure_custom_pattern(p) );
-
-            // Set staggered mode
-            FAPI_TRY( mss::rc::change_staggered_pattern(p) );
-
-            // Set custom read centering mode
-            FAPI_TRY( mss::dp16::setup_custom_read_centering_mode(p), "Error in p9_mss_draminit_training %s",
-                      mss::c_str(i_target) );
-
             // Get our rank pairs.
             FAPI_TRY( mss::rank::get_rank_pairs(p, l_pairs), "Error in p9_mss_draminit_training" );
 
@@ -136,63 +120,11 @@ extern "C"
             // THE PROCESSING OF THE ERRORS. (it's hard to figure out which DIMM failed, too) BRS.
             for (const auto& rp : l_pairs)
             {
-                bool l_cal_fail = false;
-
-                // Save off registers in case adv training fails
-                mss::dp16::rd_ctr_settings<TARGET_TYPE_MCA> l_original_settings(p, rp);
-                FAPI_TRY( l_original_settings.save() );
-
-                std::vector<fapi2::ReturnCode> l_fails_on_rp;
-
                 // Loop through all of the steps (should just be initial pattern write and custom read centering)
                 for(const auto l_step : l_steps)
                 {
                     FAPI_TRY( l_step->execute(p, rp, l_cal_abort_on_error) );
                 }
-
-                FAPI_TRY( mss::find_and_log_cal_errors(p, rp, l_cal_abort_on_error, l_cal_fail, l_fails_on_rp) );
-
-                // If we got a fail, let's ignore the previous fails and run backup pattern
-                if (l_fails_on_rp.size() != 0)
-                {
-                    l_cal_fail = false;
-                    l_fails_on_rp.clear();
-
-                    // Clear the disable bits from last run.
-                    // This function restores bad_bits to how the attribute has them
-                    // (which was updated at the end of regular training)
-                    // So we won't run on known bad bits, but will rerun on the iffy bits from last custom_pattern run
-                    FAPI_TRY( mss::dp16::reset_bad_bits( p ) );
-                    FAPI_INF("%s rp%x running back up pattern for draminit_training_adv", mss::c_str(p), rp);
-
-                    // Clear the cal errors so we can retry
-                    FAPI_TRY(mss::clear_initial_cal_errors(p), "%s error resetting errors prior to init cal", mss::c_str(p));
-
-                    fapi2::buffer<uint32_t> l_backup;
-                    FAPI_TRY( mss::custom_training_adv_backup_patterns( p, l_backup) );
-
-                    // Put the backup into the registers
-                    FAPI_TRY( mss::seq::setup_rd_wr_data( p, l_backup) );
-
-                    // Rerun the training for this rp
-                    // Loop through all of the steps (should just be initial pattern write and custom read centering)
-                    for(const auto l_step : l_steps)
-                    {
-                        FAPI_TRY( l_step->execute(p, rp, l_cal_abort_on_error) );
-                    }
-
-                    FAPI_TRY( mss::find_and_log_cal_errors(p, rp, l_cal_abort_on_error, l_cal_fail, l_fails_on_rp) );
-
-                    // If we got fails from the backup pattern, restore the pre-adv training settings for this rank pair
-                    if (l_fails_on_rp.size() != 0)
-                    {
-                        l_fails_on_rp.clear();
-                        FAPI_INF("%s rp%d draminit_training_adv failed. Restoring original settings", mss::c_str(p), rp);
-
-                        // Restore pre-training_adv settings
-                        FAPI_TRY( l_original_settings.restore() );
-                    }
-                }
             }// rank pairs
 
             // Resetting current_err.
diff --git a/src/import/chips/p9/procedures/hwp/memory/p9_mss_eff_config.C b/src/import/chips/p9/procedures/hwp/memory/p9_mss_eff_config.C
index 4b508ede7..e74dd5fbc 100644
--- a/src/import/chips/p9/procedures/hwp/memory/p9_mss_eff_config.C
+++ b/src/import/chips/p9/procedures/hwp/memory/p9_mss_eff_config.C
@@ -341,6 +341,8 @@ fapi2::ReturnCode p9_mss_eff_config( const fapi2::Target<fapi2::TARGET_TYPE_MCS>
                   "Failed cal_step_enable for %s", mss::c_str(l_dimm) );
         FAPI_TRY( l_eff_dimm->rdvref_enable_bit(),
                   "Failed rdvref_enable_bit for %s", mss::c_str(l_dimm) );
+        FAPI_TRY( l_eff_dimm->training_adv_wr_pattern(),
+                  "Failed training_adv_wr_pattern for %s", mss::c_str(l_dimm) );
         FAPI_TRY( l_eff_dimm->training_adv_pattern(),
                   "Failed training_adv_pattern for %s", mss::c_str(l_dimm) );
         FAPI_TRY( l_eff_dimm->training_adv_backup_pattern(),