Add API for MC to C4 DQ pin index translation

Change-Id: I0ca28c7f5d6c77e100cd1fdc22f7372335e369a6
CQ: SW414486
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/52658
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: STEPHEN GLANCY <sglancy@us.ibm.com>
Reviewed-by: ANDRE A. MARIN <aamarin@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/52665
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Reviewed-by: William G. Hoffa <wghoffa@us.ibm.com>

2 files changed, 163 insertions, 0 deletions

diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/rosetta_map/rosetta_map.C b/src/import/chips/p9/procedures/hwp/memory/lib/rosetta_map/rosetta_map.C
index 359c77c20..83701b9cf 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/rosetta_map/rosetta_map.C
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/rosetta_map/rosetta_map.C
@@ -37,6 +37,7 @@
 // *HWP Consumed by: FSP:HB
 
 #include <rosetta_map.H>
+#include <lib/phy/dp16.H>
 
 namespace mss
 {
@@ -400,4 +401,80 @@ const std::vector<std::pair<uint64_t, uint64_t>> rosettaTraits<fapi2::TARGET_TYP
     {3, 22}, {4, 18},
 };
 
+namespace rosetta_map
+{
+
+///
+/// @brief Given a memory controller DQ pin index, return the PHY DP16 instance and lane
+/// @tparam T fapi2 Target Type - derived
+/// @param[in] i_target the fapi2 target of the port
+/// @param[in] i_mc_pin the index of the memory controller pin
+/// @param[out] o_dp the DP instance
+/// @param[out] o_lane the lane index
+/// @return FAPI2_RC_SUCCESS iff ok
+///
+template<>
+fapi2::ReturnCode mc_to_phy<DQ>( const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target,
+                                 const uint64_t i_mc_pin,
+                                 uint64_t& o_dp,
+                                 uint64_t& o_lane )
+{
+    FAPI_ASSERT(i_mc_pin < MAX_DQ_BITS,
+                fapi2::MSS_MC_PIN_OUT_OF_RANGE()
+                .set_MCA_TARGET(i_target)
+                .set_INDEX(i_mc_pin),
+                "%s Memory controller pin type DQ, index %d is beyond maximum value %d", mss::c_str(i_target), i_mc_pin,
+                (MAX_DQ_BITS - 1) );
+
+    o_dp   = i_mc_pin / BITS_PER_DP;
+    o_lane = i_mc_pin % BITS_PER_DP;
+
+    FAPI_INF("%s MC DQ pin %d maps to PHY DP%d lane %d", mss::c_str(i_target), i_mc_pin, o_dp, o_lane);
+
+    return fapi2::FAPI2_RC_SUCCESS;
+
+fapi_try_exit:
+    return fapi2::current_err;
+}
+
+///
+/// @brief Given a PHY DP16 instance and lane, return the corresponding memory controller DQ pin index
+/// @tparam T fapi2 Target Type - derived
+/// @param[in] i_target the fapi2 target of the port
+/// @param[in] i_dp the DP instance
+/// @param[in] i_lane the lane index
+/// @param[out] o_mc_pin the index of the memory controller pin
+/// @return FAPI2_RC_SUCCESS iff ok
+///
+template<>
+fapi2::ReturnCode phy_to_mc<DQ>( const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target,
+                                 const uint64_t i_dp,
+                                 const uint64_t i_lane,
+                                 uint64_t& o_mc_pin )
+{
+    typedef mss::dp16Traits<fapi2::TARGET_TYPE_MCA> TT;
+
+    // DP4 has fewer DQ than the others
+    constexpr uint64_t BITS_ON_DP4 = 8;
+    const uint64_t l_num_dq = (i_dp == TT::DP_COUNT - 1) ? BITS_ON_DP4 : BITS_PER_DP;
+
+    FAPI_ASSERT((i_dp < TT::DP_COUNT) && (i_lane < l_num_dq),
+                fapi2::MSS_NO_MC_PIN_MAPPING()
+                .set_MCA_TARGET(i_target)
+                .set_DP(i_dp)
+                .set_LANE(i_lane),
+                "%s No memory controller pin mapping found for type DQ, DP %d, lane %d", mss::c_str(i_target), i_dp, i_lane );
+
+    o_mc_pin = (i_dp * BITS_PER_DP) + i_lane;
+
+    FAPI_INF("%s PHY DP%d lane %d maps to MC DQ pin %d", mss::c_str(i_target), i_dp, i_lane, o_mc_pin);
+
+    return fapi2::FAPI2_RC_SUCCESS;
+
+fapi_try_exit:
+    return fapi2::current_err;
+}
+
+} // ns rosetta_map
+
 } // ns mss
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/rosetta_map/rosetta_map.H b/src/import/chips/p9/procedures/hwp/memory/lib/rosetta_map/rosetta_map.H
index dc0dc3ff7..f02ff4310 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/rosetta_map/rosetta_map.H
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/rosetta_map/rosetta_map.H
@@ -369,6 +369,9 @@ fapi2::ReturnCode c4_to_phy( const fapi2::Target<T>& i_target,
     o_dp   = l_mapping[i_c4_pin].first;
     o_lane = l_mapping[i_c4_pin].second;
 
+    FAPI_INF("%s Module C4 pin type %s, index %d maps to PHY DP%d lane %d", mss::c_str(i_target), l_str_buffer, i_c4_pin,
+             o_dp, o_lane);
+
     return fapi2::FAPI2_RC_SUCCESS;
 
 fapi_try_exit:
@@ -411,12 +414,95 @@ fapi2::ReturnCode phy_to_c4( const fapi2::Target<T>& i_target,
 
     o_c4_pin = l_it - l_mapping.begin();
 
+    FAPI_INF("%s PHY DP%d lane %d (type %s) maps to module C4 pin index %d", mss::c_str(i_target), i_dp, i_lane,
+             l_str_buffer, o_c4_pin);
+
     return fapi2::FAPI2_RC_SUCCESS;
 
 fapi_try_exit:
     return fapi2::current_err;
 }
 
+///
+/// @brief Given a memory controller pin index, return the PHY DP16 instance and lane
+/// @tparam R rosetta_type enumeration of signal/pin to map
+/// @tparam T fapi2 Target Type - derived
+/// @param[in] i_target the fapi2 target of the port
+/// @param[in] i_mc_pin the index of the memory controller pin
+/// @param[out] o_dp the DP instance
+/// @param[out] o_lane the lane index
+/// @return FAPI2_RC_SUCCESS iff ok
+///
+template< rosetta_type R, fapi2::TargetType T >
+fapi2::ReturnCode mc_to_phy( const fapi2::Target<T>& i_target,
+                             const uint64_t i_mc_pin,
+                             uint64_t& o_dp,
+                             uint64_t& o_lane );
+
+///
+/// @brief Given a PHY DP16 instance and lane, return the corresponding memory controller pin index
+/// @tparam R rosetta_type enumeration of signal/pin to map
+/// @tparam T fapi2 Target Type - derived
+/// @param[in] i_target the fapi2 target of the port
+/// @param[in] i_dp the DP instance
+/// @param[in] i_lane the lane index
+/// @param[out] o_mc_pin the index of the memory controller pin
+/// @return FAPI2_RC_SUCCESS iff ok
+///
+template< rosetta_type R, fapi2::TargetType T >
+fapi2::ReturnCode phy_to_mc( const fapi2::Target<T>& i_target,
+                             const uint64_t i_dp,
+                             const uint64_t i_lane,
+                             uint64_t& o_mc_pin );
+
+///
+/// @brief Given a memory controller pin index, return the module C4 pin index
+/// @tparam R rosetta_type enumeration of signal/pin to map
+/// @tparam T fapi2 Target Type - derived
+/// @param[in] i_target the fapi2 target of the port
+/// @param[in] i_mc_pin the index of the memory controller pin
+/// @param[out] o_c4_pin the index of the module C4 pin
+/// @return FAPI2_RC_SUCCESS iff ok
+///
+template< rosetta_type R, fapi2::TargetType T >
+fapi2::ReturnCode mc_to_c4( const fapi2::Target<T>& i_target,
+                            const uint64_t i_mc_pin,
+                            uint64_t& o_c4_pin )
+{
+    uint64_t l_dp = 0;
+    uint64_t l_lane = 0;
+
+    FAPI_TRY(mc_to_phy<R>(i_target, i_mc_pin, l_dp, l_lane));
+    FAPI_TRY(phy_to_c4<R>(i_target, l_dp, l_lane, o_c4_pin));
+
+fapi_try_exit:
+    return fapi2::current_err;
+}
+
+///
+/// @brief Given a module C4 pin index, return the corresponding memory controller pin index
+/// @tparam R rosetta_type enumeration of signal/pin to map
+/// @tparam T fapi2 Target Type - derived
+/// @param[in] i_target the fapi2 target of the port
+/// @param[in] i_c4_pin the index of the module C4 pin
+/// @param[out] o_mc_pin the index of the memory controller pin
+/// @return FAPI2_RC_SUCCESS iff ok
+///
+template< rosetta_type R, fapi2::TargetType T >
+fapi2::ReturnCode c4_to_mc( const fapi2::Target<T>& i_target,
+                            const uint64_t i_c4_pin,
+                            uint64_t& o_mc_pin )
+{
+    uint64_t l_dp = 0;
+    uint64_t l_lane = 0;
+
+    FAPI_TRY(c4_to_phy<R>(i_target, i_c4_pin, l_dp, l_lane));
+    FAPI_TRY(phy_to_mc<R>(i_target, l_dp, l_lane, o_mc_pin));
+
+fapi_try_exit:
+    return fapi2::current_err;
+}
+
 } // close namespace rosetta_map
 } // close namespace mss