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author | Ben Gass <bgass@us.ibm.com> | 2016-05-18 13:01:57 -0500 |
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committer | Daniel M. Crowell <dcrowell@us.ibm.com> | 2016-06-01 14:37:49 -0400 |
commit | b1ed58c10721fe1ec98dd537929a2942e08765d0 (patch) | |
tree | 11574d41a6edf70d1ed7d24ef8e1e3b05a2aa21b /src/import/chips/p9/procedures/hwp/memory | |
parent | 0990c2c96fc3baed7908e855bacaa854b2210d0b (diff) | |
download | talos-hostboot-b1ed58c10721fe1ec98dd537929a2942e08765d0.tar.gz talos-hostboot-b1ed58c10721fe1ec98dd537929a2942e08765d0.zip |
Translate logical mca regisers in mcs chiplet as mca target type
Fixup memory code which uses the xlt registers
Add dependent epsilon inits
Change-Id: I995bcd895a0a7a431dcf350475fd387be70749c9
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/24733
Reviewed-by: Brian R. Silver <bsilver@us.ibm.com>
Tested-by: Jenkins Server
Tested-by: PPE CI
Tested-by: Hostboot CI
Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
Dev-Ready: Benjamin Gass <bgass@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/24734
Tested-by: FSP CI Jenkins
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Diffstat (limited to 'src/import/chips/p9/procedures/hwp/memory')
-rw-r--r-- | src/import/chips/p9/procedures/hwp/memory/lib/mc/mc.C | 37 | ||||
-rw-r--r-- | src/import/chips/p9/procedures/hwp/memory/lib/mc/mc.H | 9 | ||||
-rw-r--r-- | src/import/chips/p9/procedures/hwp/memory/lib/mc/xlate.C | 14 |
3 files changed, 5 insertions, 55 deletions
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/mc/mc.C b/src/import/chips/p9/procedures/hwp/memory/lib/mc/mc.C index ae8b9e61e..71b75fcaa 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/mc/mc.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/mc/mc.C @@ -40,10 +40,6 @@ using fapi2::TARGET_TYPE_MCS; namespace mss { -const uint64_t mcTraits<TARGET_TYPE_MCS>::xlate0_reg[] = {MCS_PORT02_MCP0XLT0, MCS_PORT13_MCP0XLT0}; -const uint64_t mcTraits<TARGET_TYPE_MCS>::xlate1_reg[] = {MCS_PORT02_MCP0XLT1, MCS_PORT13_MCP0XLT1}; -const uint64_t mcTraits<TARGET_TYPE_MCS>::xlate2_reg[] = {MCS_PORT02_MCP0XLT2, MCS_PORT13_MCP0XLT2}; - /// /// @brief Dump the registers of the MC (MCA_MBA, MCS) /// @param[in] i_target the MCS target @@ -126,39 +122,6 @@ fapi2::ReturnCode dump_regs( const fapi2::Target<TARGET_TYPE_MCS>& i_target ) {"MCS_MCSYNC", MCS_MCSYNC }, {"MCS_MCTO", MCS_MCTO }, {"MCS_MCWATCNTL", MCS_MCWATCNTL }, - - {"MCS_PORT02_AACR", MCS_PORT02_AACR }, - {"MCS_PORT02_AADR", MCS_PORT02_AADR }, - {"MCS_PORT02_AAER", MCS_PORT02_AAER }, - {"MCS_PORT02_MCAMOC", MCS_PORT02_MCAMOC }, - {"MCS_PORT02_MCBUSYQ", MCS_PORT02_MCBUSYQ }, - {"MCS_PORT02_MCEBUSCL", MCS_PORT02_MCEBUSCL }, - {"MCS_PORT02_MCEPSQ", MCS_PORT02_MCEPSQ }, - {"MCS_PORT02_MCERRINJ", MCS_PORT02_MCERRINJ }, - {"MCS_PORT02_MCP0XLT0", MCS_PORT02_MCP0XLT0 }, - {"MCS_PORT02_MCP0XLT1", MCS_PORT02_MCP0XLT1 }, - {"MCS_PORT02_MCP0XLT2", MCS_PORT02_MCP0XLT2 }, - {"MCS_PORT02_MCPERF0", MCS_PORT02_MCPERF0 }, - {"MCS_PORT02_MCPERF2", MCS_PORT02_MCPERF2 }, - {"MCS_PORT02_MCPERF3", MCS_PORT02_MCPERF3 }, - {"MCS_PORT02_MCWAT", MCS_PORT02_MCWAT }, - - {"MCS_PORT13_MCAMOC", MCS_PORT13_MCAMOC }, - {"MCS_PORT13_MCBUSYQ", MCS_PORT13_MCBUSYQ }, - {"MCS_PORT13_MCEBUSCL", MCS_PORT13_MCEBUSCL }, - {"MCS_PORT13_MCEBUSEN0", MCS_PORT13_MCEBUSEN0 }, - {"MCS_PORT13_MCEBUSEN1", MCS_PORT13_MCEBUSEN1 }, - {"MCS_PORT13_MCEBUSEN2", MCS_PORT13_MCEBUSEN2 }, - {"MCS_PORT13_MCEBUSEN3", MCS_PORT13_MCEBUSEN3 }, - {"MCS_PORT13_MCEPSQ", MCS_PORT13_MCEPSQ }, - {"MCS_PORT13_MCERRINJ", MCS_PORT13_MCERRINJ }, - {"MCS_PORT13_MCP0XLT0", MCS_PORT13_MCP0XLT0 }, - {"MCS_PORT13_MCP0XLT1", MCS_PORT13_MCP0XLT1 }, - {"MCS_PORT13_MCP0XLT2", MCS_PORT13_MCP0XLT2 }, - {"MCS_PORT13_MCPERF0", MCS_PORT13_MCPERF0 }, - {"MCS_PORT13_MCPERF2", MCS_PORT13_MCPERF2 }, - {"MCS_PORT13_MCPERF3", MCS_PORT13_MCPERF3 }, - {"MCS_PORT13_MCWAT", MCS_PORT13_MCWAT }, }; for (auto r : l_mcs_registers) diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/mc/mc.H b/src/import/chips/p9/procedures/hwp/memory/lib/mc/mc.H index 7416b96dd..ac52592f6 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/mc/mc.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/mc/mc.H @@ -56,7 +56,7 @@ class mcTraits; /// @brief a collection of traits associated with the Centaur controller /// template<> -class mcTraits<fapi2::TARGET_TYPE_MEMBUF_CHIP> +class mcTraits<fapi2::TARGET_TYPE_MBA> { }; @@ -65,14 +65,9 @@ class mcTraits<fapi2::TARGET_TYPE_MEMBUF_CHIP> /// @brief a collection of traits associated with the Nimbus controller /// template<> -class mcTraits<fapi2::TARGET_TYPE_MCS> +class mcTraits<fapi2::TARGET_TYPE_MCA> { public: - // Array of registers indexed by MCA position - static const uint64_t xlate0_reg[2]; - static const uint64_t xlate1_reg[2]; - static const uint64_t xlate2_reg[2]; - enum { SLOT0_VALID = MCS_PORT02_MCP0XLT0_SLOT0_VALID, diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/mc/xlate.C b/src/import/chips/p9/procedures/hwp/memory/lib/mc/xlate.C index 69b2bd568..a08ca3b09 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/mc/xlate.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/mc/xlate.C @@ -70,14 +70,6 @@ fapi2::ReturnCode mc<TARGET_TYPE_MCS>::setup_xlate_map(const fapi2::Target<TARGE FAPI_INF("Setting up xlate registers for MCA%d (%d)", mss::pos(i_target), mss::index(i_target)); - // The addressing for the xlt registers is funky. We have a different unit0 address for units 0/2 - // than we do for 1/3. - const uint64_t& l_t0_address = mss::pos(i_target) % 2 ? MCS_0_PORT13_MCP0XLT0 : MCS_0_PORT02_MCP0XLT0; - const uint64_t& l_t1_address = mss::pos(i_target) % 2 ? MCS_0_PORT13_MCP0XLT1 : MCS_0_PORT02_MCP0XLT1; - const uint64_t& l_t2_address = mss::pos(i_target) % 2 ? MCS_0_PORT13_MCP0XLT2 : MCS_0_PORT02_MCP0XLT2; - - FAPI_DBG("xlate scoms registers 0x%016lx, 0x%016lx, 0x%016lx", l_t0_address, l_t1_address, l_t2_address); - // We enable the DIMM select bit for slot1 if we have two DIMM installed l_xlate.writeBit<MCS_PORT13_MCP0XLT0_SLOT1_D_VALUE>(l_dimms.size() == 2); @@ -213,9 +205,9 @@ fapi2::ReturnCode mc<TARGET_TYPE_MCS>::setup_xlate_map(const fapi2::Target<TARGE FAPI_DBG("HACK: Cramming 0x%016lx in for MCP0XLT1", l_xlate1); FAPI_DBG("HACK: Cramming 0x%016lx in for MCP0XLT2", l_xlate2); - FAPI_TRY( mss::putScom(i_target.getParent<TARGET_TYPE_MCS>(), l_t0_address, l_xlate) ); - FAPI_TRY( mss::putScom(i_target.getParent<TARGET_TYPE_MCS>(), l_t1_address, l_xlate1) ); - FAPI_TRY( mss::putScom(i_target.getParent<TARGET_TYPE_MCS>(), l_t2_address, l_xlate2) ); + FAPI_TRY( mss::putScom(i_target, MCA_MBA_MCP0XLT0, l_xlate) ); + FAPI_TRY( mss::putScom(i_target, MCA_MBA_MCP0XLT1, l_xlate1) ); + FAPI_TRY( mss::putScom(i_target, MCA_MBA_MCP0XLT2, l_xlate2) ); fapi_try_exit: return fapi2::current_err; |