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| author | Brian Silver <bsilver@us.ibm.com> | 2016-01-31 05:38:14 -0600 |
|---|---|---|
| committer | Daniel M. Crowell <dcrowell@us.ibm.com> | 2016-02-22 10:15:17 -0600 |
| commit | 4b388bf1604d073c420e5047c96ccd16cdd6a2c1 (patch) | |
| tree | 8f08961ca57a502ee4f35ef6efc9754580dbdae4 /src/import/chips/p9/procedures/hwp/memory | |
| parent | 7f5e1ff0a70bd89fa4b496ea130a5045e5fafe7d (diff) | |
| download | talos-hostboot-4b388bf1604d073c420e5047c96ccd16cdd6a2c1.tar.gz talos-hostboot-4b388bf1604d073c420e5047c96ccd16cdd6a2c1.zip | |
Add dump_regs for MC
Change-Id: Ifed6fb999c6f037a1e01281b0acd8f3d8a9dffc2
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/23812
Tested-by: Jenkins Server
Reviewed-by: Andre A. Marin <aamarin@us.ibm.com>
Reviewed-by: Craig C. Hamilton <cchamilt@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/24531
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Diffstat (limited to 'src/import/chips/p9/procedures/hwp/memory')
| -rw-r--r-- | src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit_mc.C | 11 |
1 files changed, 9 insertions, 2 deletions
diff --git a/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit_mc.C b/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit_mc.C index 0d9c7342e..ed2b00e89 100644 --- a/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit_mc.C +++ b/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit_mc.C @@ -7,7 +7,7 @@ /* */ /* EKB Project */ /* */ -/* COPYRIGHT 2015 */ +/* COPYRIGHT 2015,2016 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -34,6 +34,7 @@ using fapi2::TARGET_TYPE_MCBIST; using fapi2::TARGET_TYPE_MCA; +using fapi2::TARGET_TYPE_MCS; extern "C" { @@ -55,12 +56,18 @@ extern "C" return fapi2::FAPI2_RC_SUCCESS; } + // Dump the registers of these MC + for (auto c : i_target.getChildren<TARGET_TYPE_MCS>()) + { + FAPI_TRY( mss::dump_regs<TARGET_TYPE_MCS>(c) ); + } + for (auto p : l_mca) { // Set the IML Complete bit MBSSQ(3) (SCOM Addr: 0x02011417) to indicate that IML has completed // Can't find MBSSQ or the iml_complete bit - asked Steve BRS. - // Reset addr_mux_sel to “0” to allow the MBA to take control of the DDR interface over from CCS. + // Reset addr_mux_sel to “0” to allow the MCA to take control of the DDR interface over from CCS. // (Note: this step must remain in this procedure to ensure that data path is placed into mainline // mode prior to running memory diagnostics. When Advanced DRAM Training executes, this step // becomes superfluous but not harmful. However, it's not guaranteed that Advanced DRAM Training |
