diff options
author | Ben Gass <bgass@us.ibm.com> | 2018-09-13 15:34:01 -0500 |
---|---|---|
committer | Christian R. Geddes <crgeddes@us.ibm.com> | 2018-11-20 17:48:04 -0600 |
commit | 3f1f2186bb80322594a3cc81241c390119d69552 (patch) | |
tree | 7ab9514c3431a99f846658376b438523a0573a71 /src/import/chips/p9/procedures/hwp/memory/p9a_omi_init.C | |
parent | 499916e4586920a5342a64646f3f2ec4bbe4e19d (diff) | |
download | talos-hostboot-3f1f2186bb80322594a3cc81241c390119d69552.tar.gz talos-hostboot-3f1f2186bb80322594a3cc81241c390119d69552.zip |
Adding omi_init procedures.
Change-Id: I176be8901393d62cee0173568e538565444eac01
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/66094
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Reviewed-by: STEPHEN GLANCY <sglancy@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/67326
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>
Diffstat (limited to 'src/import/chips/p9/procedures/hwp/memory/p9a_omi_init.C')
-rw-r--r-- | src/import/chips/p9/procedures/hwp/memory/p9a_omi_init.C | 140 |
1 files changed, 140 insertions, 0 deletions
diff --git a/src/import/chips/p9/procedures/hwp/memory/p9a_omi_init.C b/src/import/chips/p9/procedures/hwp/memory/p9a_omi_init.C index b20793648..b11696597 100644 --- a/src/import/chips/p9/procedures/hwp/memory/p9a_omi_init.C +++ b/src/import/chips/p9/procedures/hwp/memory/p9a_omi_init.C @@ -31,3 +31,143 @@ // *HWP Team: // *HWP Level: 2 // *HWP Consumed by: HB + +#include <p9a_omi_init.H> +#include <p9a_omi_init_scom.H> +#include <p9a_mc_scom_addresses.H> +#include <p9a_mc_scom_addresses_fld.H> + +/// +/// @brief Run initfile to enable templates and set pacing. +/// +/// @param[in] i_target p9a channel to work on +/// +/// @return fapi2:ReturnCode. FAPI2_RC_SUCCESS if success, else error code. +/// +fapi2::ReturnCode p9a_omi_init_scominit(const fapi2::Target<fapi2::TARGET_TYPE_MCC>& i_target) +{ + fapi2::ReturnCode l_rc; + const fapi2::Target<fapi2::TARGET_TYPE_SYSTEM> FAPI_SYSTEM; + + FAPI_EXEC_HWP(l_rc, p9a_omi_init_scom, i_target, FAPI_SYSTEM); + + if (l_rc) + { + FAPI_ERR("Error from p9a.omi_init.scom.initfile"); + fapi2::current_err = l_rc; + } + + FAPI_DBG("Exiting with return code : %08X...", (uint64_t) fapi2::current_err); + return fapi2::current_err; +} + +/// +/// @brief Check and enable supported templates +/// +/// @param[in] i_target p9a channel to work on +/// +/// @return fapi2:ReturnCode. FAPI2_RC_SUCCESS if success, else error code. +/// +fapi2::ReturnCode p9a_omi_init_enable_templates(const fapi2::Target<fapi2::TARGET_TYPE_MCC>& i_target) +{ + fapi2::ATTR_PROC_ENABLE_DL_TMPL_1_Type l_enable_tmpl_1; + fapi2::ATTR_PROC_ENABLE_DL_TMPL_4_Type l_enable_tmpl_4; + fapi2::ATTR_PROC_ENABLE_DL_TMPL_7_Type l_enable_tmpl_7; + fapi2::buffer<uint64_t> l_data; + + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_ENABLE_DL_TMPL_1, + i_target, + l_enable_tmpl_1), + "Error from FAPI_ATTR_GET (ATTR_PROC_ENABLE_DL_TMPL_1)"); + + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_ENABLE_DL_TMPL_4, + i_target, + l_enable_tmpl_4), + "Error from FAPI_ATTR_GET (ATTR_PROC_ENABLE_DL_TMPL_4)"); + + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_ENABLE_DL_TMPL_7, + i_target, + l_enable_tmpl_7), + "Error from FAPI_ATTR_GET (ATTR_PROC_ENABLE_DL_TMPL_7)"); + + FAPI_ASSERT(l_enable_tmpl_1 != 0, + fapi2::PROC_DOWNSTREAM_TMPL1_REQUIRED_ERR() + .set_TARGET(i_target), + "Downstream template 1 is required."); + + FAPI_ASSERT(l_enable_tmpl_4 != 0 || l_enable_tmpl_7 != 0, + fapi2::PROC_DOWNSTREAM_TMPL4OR7_REQUIRED_ERR() + .set_TARGET(i_target), + "Downstream template 4 and/or 7 is required."); + + //Turn off temp0_only + FAPI_TRY(getScom(i_target, P9A_MCC_DSTLCFG, l_data)); + l_data.clearBit<P9A_MCC_DSTLCFG_TMPL0_ONLY>(); + FAPI_TRY(putScom(i_target, P9A_MCC_DSTLCFG, l_data)); + +fapi_try_exit: + + FAPI_DBG("Exiting with return code : %08X...", (uint64_t) fapi2::current_err); + return fapi2::current_err; +} + +/// +/// @brief Enable ibm buffer chip low latency mode +/// +/// @param[in] i_target p9a channel to work on +/// +/// @return fapi2:ReturnCode. FAPI2_RC_SUCCESS if success, else error code. +/// +fapi2::ReturnCode p9a_omi_init_enable_lol(const fapi2::Target<fapi2::TARGET_TYPE_MCC>& i_target) +{ + fapi2::buffer<uint64_t> l_data; + std::vector<fapi2::Target<fapi2::TARGET_TYPE_OMI>> l_omi_targets; + fapi2::ATTR_CHIP_UNIT_POS_Type l_omi_pos; + + + l_omi_targets = i_target.getChildren<fapi2::TARGET_TYPE_OMI>(); + + FAPI_TRY(getScom(i_target, P9A_MCC_USTLCFG, l_data)); + + for (const auto l_omi_target : l_omi_targets) + { + FAPI_TRY(FAPI_ATTR_GET( fapi2::ATTR_CHIP_UNIT_POS, + l_omi_target, + l_omi_pos)); + + if ((l_omi_pos % 2) == 0) + { + l_data.setBit<P9A_MCC_USTLCFG_IBM_BUFFER_CHIP_CHANA_ENABLE>(); + } + else + { + l_data.setBit<P9A_MCC_USTLCFG_IBM_BUFFER_CHIP_CHANB_ENABLE>(); + } + } + + FAPI_TRY(putScom(i_target, P9A_MCC_USTLCFG, l_data)); + +fapi_try_exit: + + FAPI_DBG("Exiting with return code : %08X...", (uint64_t) fapi2::current_err); + return fapi2::current_err; +} + +/// +/// @brief Finalize the OMI +/// +/// @param[in] i_target p9a channel to work on +/// +/// @return fapi2:ReturnCode. FAPI2_RC_SUCCESS if success, else error code. +/// +fapi2::ReturnCode p9a_omi_init(const fapi2::Target<fapi2::TARGET_TYPE_MCC>& i_target) +{ + FAPI_TRY(p9a_omi_init_scominit(i_target)); + FAPI_TRY(p9a_omi_init_enable_templates(i_target)); + FAPI_TRY(p9a_omi_init_enable_lol(i_target)); + +fapi_try_exit: + + FAPI_DBG("Exiting with return code : %08X...", (uint64_t) fapi2::current_err); + return fapi2::current_err; +} |