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| author | Brian Silver <bsilver@us.ibm.com> | 2016-04-25 09:24:34 -0500 |
|---|---|---|
| committer | Daniel M. Crowell <dcrowell@us.ibm.com> | 2016-05-03 18:36:19 -0400 |
| commit | 1c3233db39fad9fe7e4799f65823bf115afb872d (patch) | |
| tree | 4ec58fb047822ee2af3a853e11afc818295848ad /src/import/chips/p9/procedures/hwp/memory/p9_mss_scrub.C | |
| parent | 8ef2e43b09194df457a8cf44978117637a054238 (diff) | |
| download | talos-hostboot-1c3233db39fad9fe7e4799f65823bf115afb872d.tar.gz talos-hostboot-1c3233db39fad9fe7e4799f65823bf115afb872d.zip | |
Add 8Gb DRAM support
Change-Id: Ia2ba89169b1bdfe746bce29f5e6c32ef14b2e11c
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/23720
Tested-by: Jenkins Server
Tested-by: Hostboot CI
Reviewed-by: Louis Stermole <stermole@us.ibm.com>
Reviewed-by: JACOB L. HARVEY <jlharvey@us.ibm.com>
Reviewed-by: STEPHEN GLANCY <sglancy@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/23722
Tested-by: FSP CI Jenkins
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Diffstat (limited to 'src/import/chips/p9/procedures/hwp/memory/p9_mss_scrub.C')
| -rw-r--r-- | src/import/chips/p9/procedures/hwp/memory/p9_mss_scrub.C | 24 |
1 files changed, 14 insertions, 10 deletions
diff --git a/src/import/chips/p9/procedures/hwp/memory/p9_mss_scrub.C b/src/import/chips/p9/procedures/hwp/memory/p9_mss_scrub.C index 85a221a37..da0552a9b 100644 --- a/src/import/chips/p9/procedures/hwp/memory/p9_mss_scrub.C +++ b/src/import/chips/p9/procedures/hwp/memory/p9_mss_scrub.C @@ -73,6 +73,9 @@ fapi2::ReturnCode p9_mss_scrub( const fapi2::Target<TARGET_TYPE_MCBIST>& i_targe // Setup l_start to represent this rank, and then make the end address from that. l_start.set_master_rank(r); + // For checking 8Gb DRAM, add row 16 to the mix - should see valid traffic in the AET + l_start.set_row(0b10); + // l_end starts like as the max as we want to scrub the entire thing. If we're in sim, // we'll wratchet that back. l_start.get_range<mss::mcbist::address::MRANK>(l_end); @@ -86,7 +89,8 @@ fapi2::ReturnCode p9_mss_scrub( const fapi2::Target<TARGET_TYPE_MCBIST>& i_targe // By default we're in maint address mode, not address counting mode. So we give it a start and end, and ignore // anything invalid - that's what maint address mode is all about - mss::mcbist::config_address_range(i_target, l_start, l_end, r); +// mss::mcbist::config_address_range(i_target, l_start, l_end, r); + mss::mcbist::config_address_range(i_target, l_start, l_start + 4, r); // Write { @@ -116,15 +120,15 @@ fapi2::ReturnCode p9_mss_scrub( const fapi2::Target<TARGET_TYPE_MCBIST>& i_targe } } - // Write 0's - FAPI_TRY( mss::putScom(i_target, MCBIST_MCBFD0Q, 0) ); - FAPI_TRY( mss::putScom(i_target, MCBIST_MCBFD1Q, 0) ); - FAPI_TRY( mss::putScom(i_target, MCBIST_MCBFD2Q, 0) ); - FAPI_TRY( mss::putScom(i_target, MCBIST_MCBFD3Q, 0) ); - FAPI_TRY( mss::putScom(i_target, MCBIST_MCBFD4Q, 0) ); - FAPI_TRY( mss::putScom(i_target, MCBIST_MCBFD5Q, 0) ); - FAPI_TRY( mss::putScom(i_target, MCBIST_MCBFD6Q, 0) ); - FAPI_TRY( mss::putScom(i_target, MCBIST_MCBFD7Q, 0) ); + // Write pattern + FAPI_TRY( mss::putScom(i_target, MCBIST_MCBFD0Q, 0x1234567890ABCDEF) ); + FAPI_TRY( mss::putScom(i_target, MCBIST_MCBFD1Q, 0x1234567890ABCDEF) ); + FAPI_TRY( mss::putScom(i_target, MCBIST_MCBFD2Q, 0x1234567890ABCDEF) ); + FAPI_TRY( mss::putScom(i_target, MCBIST_MCBFD3Q, 0x1234567890ABCDEF) ); + FAPI_TRY( mss::putScom(i_target, MCBIST_MCBFD4Q, 0x1234567890ABCDEF) ); + FAPI_TRY( mss::putScom(i_target, MCBIST_MCBFD5Q, 0x1234567890ABCDEF) ); + FAPI_TRY( mss::putScom(i_target, MCBIST_MCBFD6Q, 0x1234567890ABCDEF) ); + FAPI_TRY( mss::putScom(i_target, MCBIST_MCBFD7Q, 0x1234567890ABCDEF) ); // Setup the sim polling based on a heuristic <cough>guess</cough> // Looks like ~250ck per address for a write/read program on the sim-dimm, and add a long number of polls |
