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| author | Stephen Glancy <sglancy@us.ibm.com> | 2016-08-04 16:41:45 -0500 |
|---|---|---|
| committer | Daniel M. Crowell <dcrowell@us.ibm.com> | 2016-08-06 23:09:25 -0400 |
| commit | 16b5ea836e4fb7ba3daace47685b257e6f6a5a70 (patch) | |
| tree | 4a9cd7c2bdfa14d4574af8a21091b073b6b464bd /src/import/chips/p9/procedures/hwp/memory/p9_mss_eff_config.C | |
| parent | de883b764f70d0f8ea4ba89243daf0dcb20d8c83 (diff) | |
| download | talos-hostboot-16b5ea836e4fb7ba3daace47685b257e6f6a5a70.tar.gz talos-hostboot-16b5ea836e4fb7ba3daace47685b257e6f6a5a70.zip | |
Added WR VREF VPD functionality to eff_config
This commit updates effective config to generate attribute values for
WR VREF values from ATTR_MSS_VPD_MT_VREF_DRAM_WR. These attributes
are currrently consumed by mrs06 load.
TODO RTC:158807 - described below.
Functionality will need to be added for the initial sets of these
values for the PHY's WR VREF calibration algorithm. This
functionality is not needed for initial poweron but is needed for
DD2 RIT protect.
Change-Id: I081bea16bc3c2d2bc0779ddf2e178a02dd3e2072
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/27892
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: Louis Stermole <stermole@us.ibm.com>
Reviewed-by: ANDRE A. MARIN <aamarin@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Brian R. Silver <bsilver@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/27893
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Diffstat (limited to 'src/import/chips/p9/procedures/hwp/memory/p9_mss_eff_config.C')
| -rw-r--r-- | src/import/chips/p9/procedures/hwp/memory/p9_mss_eff_config.C | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/import/chips/p9/procedures/hwp/memory/p9_mss_eff_config.C b/src/import/chips/p9/procedures/hwp/memory/p9_mss_eff_config.C index f0e22fa98..181995b20 100644 --- a/src/import/chips/p9/procedures/hwp/memory/p9_mss_eff_config.C +++ b/src/import/chips/p9/procedures/hwp/memory/p9_mss_eff_config.C @@ -56,6 +56,9 @@ fapi2::ReturnCode p9_mss_eff_config( const fapi2::Target<fapi2::TARGET_TYPE_MCS> std::map<uint32_t, std::shared_ptr<mss::spd::decoder> > l_factory_caches; FAPI_TRY( mss::spd::populate_decoder_caches(i_target, l_factory_caches) ); + // Decode the VPD for this MCS and stick it in the attributes. + FAPI_TRY( l_eff_config.decode_vpd(i_target) ); + for( const auto& l_dimm : mss::find_targets<fapi2::TARGET_TYPE_DIMM>(i_target) ) { const auto l_dimm_pos = mss::pos(l_dimm); @@ -220,9 +223,6 @@ fapi2::ReturnCode p9_mss_eff_config( const fapi2::Target<fapi2::TARGET_TYPE_MCS> }// dimm - // Decode the VPD for this MCS and stick it in the attributes. - FAPI_TRY( l_eff_config.decode_vpd(i_target) ); - fapi_try_exit: return fapi2::current_err; } |
