diff options
| author | Louis Stermole <stermole@us.ibm.com> | 2020-01-24 10:55:11 -0500 |
|---|---|---|
| committer | Daniel M Crowell <dcrowell@us.ibm.com> | 2020-02-13 15:31:32 -0600 |
| commit | c49249c720f42d201c92ef887930fee600fa34b5 (patch) | |
| tree | a106ed8a117fcc403e520fc96ac807915b43d9d9 /src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit_mc.C | |
| parent | 97fc5523bba37078bca09dec8ddecc6724f914aa (diff) | |
| download | talos-hostboot-c49249c720f42d201c92ef887930fee600fa34b5.tar.gz talos-hostboot-c49249c720f42d201c92ef887930fee600fa34b5.zip | |
Add Explorer specific MCBIST settings before scrub and maint
Change-Id: Ieabf8b23b6670ed23664ce2f80b04012c05a4319
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/90287
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Reviewed-by: STEPHEN GLANCY <sglancy@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Dev-Ready: Louis Stermole <stermole@us.ibm.com>
Reviewed-by: ANDRE A MARIN <aamarin@us.ibm.com>
Reviewed-by: Jennifer A Stofer <stofer@us.ibm.com>
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/90317
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M Crowell <dcrowell@us.ibm.com>
Diffstat (limited to 'src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit_mc.C')
| -rw-r--r-- | src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit_mc.C | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit_mc.C b/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit_mc.C index b65c0ac00..22a6bacb4 100644 --- a/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit_mc.C +++ b/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit_mc.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2015,2019 */ +/* Contributors Listed Below - COPYRIGHT 2015,2020 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -140,10 +140,10 @@ extern "C" FAPI_TRY( mss::enable_periodic_cal(p), "%s Failed enable_periodic_cal", mss::c_str(i_target) ); // Step Six: Setup Control Bit ECC - FAPI_TRY( mss::enable_read_ecc(p), "%s Failed enable_read_ecc", mss::c_str(i_target) ); + FAPI_TRY( mss::enable_read_ecc<mss::mc_type::NIMBUS>(p), "%s Failed enable_read_ecc", mss::c_str(i_target) ); // apply marks from MVPD - FAPI_TRY( mss::apply_mark_store(p), "%s Failed enable_read_ecc", mss::c_str(i_target) ); + FAPI_TRY( mss::apply_mark_store(p), "%s Failed apply_mark_store", mss::c_str(i_target) ); } // At this point the DDR interface must be monitored for memory errors. Memory related FIRs should be unmasked. |
