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| author | Stephen Glancy <sglancy@us.ibm.com> | 2017-06-16 15:44:22 -0500 |
|---|---|---|
| committer | Daniel M. Crowell <dcrowell@us.ibm.com> | 2017-06-20 11:23:21 -0400 |
| commit | 32d63b3d13514409fc186933237238efb2d64660 (patch) | |
| tree | fa6e31264751a7cd64d2927c8dea4b27f66f9858 /src/import/chips/p9/procedures/hwp/memory/p9_mss_ddr_phy_reset.C | |
| parent | 2ba9ff874e2f66f6dc7b2c1b13f56b2806613093 (diff) | |
| download | talos-hostboot-32d63b3d13514409fc186933237238efb2d64660.tar.gz talos-hostboot-32d63b3d13514409fc186933237238efb2d64660.zip | |
Fixed DLL workarounds to always run
DLL workarounds will not be fixed in hardware,
in the foreseeable future. As such, always run the workarounds.
Change-Id: Iaa48b1b976908fdbb8af1eb8d518147fabc8cdce
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/41998
Reviewed-by: LUCAS W. MULKEY <lwmulkey@us.ibm.com>
Reviewed-by: JACOB L. HARVEY <jlharvey@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Dev-Ready: STEPHEN GLANCY <sglancy@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Matt K. Light <mklight@us.ibm.com>
Reviewed-by: Louis Stermole <stermole@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Reviewed-by: ANDRE A. MARIN <aamarin@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/42008
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Diffstat (limited to 'src/import/chips/p9/procedures/hwp/memory/p9_mss_ddr_phy_reset.C')
| -rw-r--r-- | src/import/chips/p9/procedures/hwp/memory/p9_mss_ddr_phy_reset.C | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/src/import/chips/p9/procedures/hwp/memory/p9_mss_ddr_phy_reset.C b/src/import/chips/p9/procedures/hwp/memory/p9_mss_ddr_phy_reset.C index ab6dc8548..b1ea39b4c 100644 --- a/src/import/chips/p9/procedures/hwp/memory/p9_mss_ddr_phy_reset.C +++ b/src/import/chips/p9/procedures/hwp/memory/p9_mss_ddr_phy_reset.C @@ -114,9 +114,10 @@ extern "C" FAPI_INF( "starting DLL calibration %s", mss::c_str(i_target) ); fapi2::ReturnCode l_rc = mss::dll_calibration(i_target); - // Only run DLL workaround if we fail DLL cal and we are a < DD2.0 part - if( l_rc != fapi2::FAPI2_RC_SUCCESS && - mss::chip_ec_feature_mss_dll_workaround(i_target) ) + // Only run DLL workaround if we fail DLL cal + // Note: there is no EC workaround for this workaround + // The designer team informed me that there is no hardware fix in plan for this type of fail as of DD2 - SPG + if( l_rc != fapi2::FAPI2_RC_SUCCESS ) { FAPI_INF( "%s Applying DLL workaround", mss::c_str(i_target) ); l_rc = mss::workarounds::dll::fix_bad_voltage_settings(i_target); |
